hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
Since we now support both the hypervisor and the secure physical timer, wire their interrupt lines up in the a15mpcore wrapper object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -75,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
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for (i = 0; i < s->num_cpu; i++) {
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for (i = 0; i < s->num_cpu; i++) {
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DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
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DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
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int ppibase = s->num_irq - 32 + i * 32;
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int ppibase = s->num_irq - 32 + i * 32;
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/* physical timer; we wire it up to the non-secure timer's ID,
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int irq;
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* since a real A15 always has TrustZone but QEMU doesn't.
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/* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs used on the A15:
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*/
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*/
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qdev_connect_gpio_out(cpudev, 0,
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const int timer_irq[] = {
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qdev_get_gpio_in(gicdev, ppibase + 30));
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[GTIMER_PHYS] = 30,
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/* virtual timer */
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[GTIMER_VIRT] = 27,
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qdev_connect_gpio_out(cpudev, 1,
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[GTIMER_HYP] = 26,
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qdev_get_gpio_in(gicdev, ppibase + 27));
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[GTIMER_SEC] = 29,
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};
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for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
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qdev_connect_gpio_out(cpudev, irq,
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qdev_get_gpio_in(gicdev,
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ppibase + timer_irq[irq]));
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}
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}
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}
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/* Memory map (addresses are offsets from PERIPHBASE):
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/* Memory map (addresses are offsets from PERIPHBASE):
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