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target/mips: Remove duplicated MIPSCPU::cp0_count_rate

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Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-12-13 11:06:07 +01:00
parent c8aeab3a09
commit 5e0c126aad
3 changed files with 9 additions and 19 deletions
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10
target/mips/cpu.c
View File

@ -434,13 +434,11 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
*/
#define CPU_FREQ_HZ_DEFAULT 200000000
#define CP0_COUNT_RATE_DEFAULT 2
static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
/* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
env->cpu_model->CCRes);
assert(env->cp0_count_ns);
@ -515,13 +513,6 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
return oc;
}
static Property mips_cpu_properties[] = {
/* CP0 timer running at half the clock of the CPU */
DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
CP0_COUNT_RATE_DEFAULT),
DEFINE_PROP_END_OF_LIST()
};
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
@ -561,7 +552,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
device_class_set_props(dc, mips_cpu_properties);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;

9
target/mips/cpu.h
View File

@ -1168,7 +1168,6 @@ struct CPUMIPSState {
* @env: #CPUMIPSState
* @clock: this CPU input clock (may be connected
* to an output clock from another device).
* @cp0_count_rate: rate at which the coprocessor 0 counter increments
*
* A MIPS CPU.
*/
@ -1180,14 +1179,6 @@ struct MIPSCPU {
Clock *clock;
CPUNegativeOffsetState neg;
CPUMIPSState env;
/*
* The Count register acts as a timer, incrementing at a constant rate,
* whether or not an instruction is executed, retired, or any forward
* progress is made through the pipeline. The rate at which the counter
* increments is implementation dependent, and is a function of the
* pipeline clock of the processor, not the issue width of the processor.
*/
unsigned cp0_count_rate;
};

9
target/mips/internal.h
View File

@ -46,6 +46,15 @@ struct mips_def_t {
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
/*
* @CCRes: rate at which the coprocessor 0 counter increments
*
* The Count register acts as a timer, incrementing at a constant rate,
* whether or not an instruction is executed, retired, or any forward
* progress is made through the pipeline. The rate at which the counter
* increments is implementation dependent, and is a function of the
* pipeline clock of the processor, not the issue width of the processor.
*/
int32_t CCRes;
int32_t CP0_Status_rw_bitmask;
int32_t CP0_TCStatus_rw_bitmask;