eepro100: convert to memory API
Note: the existing code aliases the flash BAR into the MMIO bar. This is probably a bug. This patch does not correct the problem. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
ad00a9b9d4
commit
5e6ffddef6
186
hw/eepro100.c
186
hw/eepro100.c
@ -228,13 +228,14 @@ typedef struct {
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PCIDevice dev;
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/* Hash register (multicast mask array, multiple individual addresses). */
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uint8_t mult[8];
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int mmio_index;
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MemoryRegion mmio_bar;
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MemoryRegion io_bar;
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MemoryRegion flash_bar;
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NICState *nic;
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NICConf conf;
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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/* region must not be saved by nic_save. */
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uint32_t region1; /* PCI region 1 address */
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uint16_t mdimem[32];
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eeprom_t *eeprom;
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uint32_t device; /* device variant */
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@ -1584,147 +1585,36 @@ static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
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}
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}
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/*****************************************************************************
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*
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* Port mapped I/O.
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*
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****************************************************************************/
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static uint32_t ioport_read1(void *opaque, uint32_t addr)
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static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s\n", regname(addr));
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#endif
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return eepro100_read1(s, addr - s->region1);
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switch (size) {
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case 1: return eepro100_read1(s, addr);
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case 2: return eepro100_read2(s, addr);
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case 4: return eepro100_read4(s, addr);
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default: abort();
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}
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}
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static uint32_t ioport_read2(void *opaque, uint32_t addr)
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static void eepro100_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned size)
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{
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EEPRO100State *s = opaque;
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return eepro100_read2(s, addr - s->region1);
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switch (size) {
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case 1: return eepro100_write1(s, addr, data);
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case 2: return eepro100_write2(s, addr, data);
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case 4: return eepro100_write4(s, addr, data);
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default: abort();
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}
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}
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static uint32_t ioport_read4(void *opaque, uint32_t addr)
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{
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EEPRO100State *s = opaque;
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return eepro100_read4(s, addr - s->region1);
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}
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static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write1(s, addr - s->region1, val);
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}
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static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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eepro100_write2(s, addr - s->region1, val);
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}
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static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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eepro100_write4(s, addr - s->region1, val);
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}
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/***********************************************************/
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/* PCI EEPRO100 definitions */
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static void pci_map(PCIDevice * pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type)
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{
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EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
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TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
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"size=0x%08"FMT_PCIBUS", type=%d\n",
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region_num, addr, size, type));
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assert(region_num == 1);
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register_ioport_write(addr, size, 1, ioport_write1, s);
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register_ioport_read(addr, size, 1, ioport_read1, s);
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register_ioport_write(addr, size, 2, ioport_write2, s);
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register_ioport_read(addr, size, 2, ioport_read2, s);
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register_ioport_write(addr, size, 4, ioport_write4, s);
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register_ioport_read(addr, size, 4, ioport_read4, s);
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s->region1 = addr;
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}
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/*****************************************************************************
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*
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* Memory mapped I/O.
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*
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****************************************************************************/
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static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write1(s, addr, val);
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}
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static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write2(s, addr, val);
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}
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static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s val=0x%02x\n", regname(addr), val);
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#endif
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eepro100_write4(s, addr, val);
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}
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static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s\n", regname(addr));
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#endif
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return eepro100_read1(s, addr);
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}
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static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s\n", regname(addr));
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#endif
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return eepro100_read2(s, addr);
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}
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static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
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{
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EEPRO100State *s = opaque;
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#if 0
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logout("addr=%s\n", regname(addr));
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#endif
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return eepro100_read4(s, addr);
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}
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static CPUWriteMemoryFunc * const pci_mmio_write[] = {
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pci_mmio_writeb,
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pci_mmio_writew,
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pci_mmio_writel
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};
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static CPUReadMemoryFunc * const pci_mmio_read[] = {
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pci_mmio_readb,
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pci_mmio_readw,
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pci_mmio_readl
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static const MemoryRegionOps eepro100_ops = {
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.read = eepro100_read,
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.write = eepro100_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int nic_can_receive(VLANClientState *nc)
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@ -1953,7 +1843,9 @@ static int pci_nic_uninit(PCIDevice *pci_dev)
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{
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EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
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cpu_unregister_io_memory(s->mmio_index);
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memory_region_destroy(&s->mmio_bar);
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memory_region_destroy(&s->io_bar);
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memory_region_destroy(&s->flash_bar);
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vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
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eeprom93xx_free(&pci_dev->qdev, s->eeprom);
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qemu_del_vlan_client(&s->nic->nc);
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@ -1985,20 +1877,20 @@ static int e100_nic_init(PCIDevice *pci_dev)
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s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
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/* Handler for memory-mapped I/O */
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s->mmio_index =
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cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
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DEVICE_LITTLE_ENDIAN);
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pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
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PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index);
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pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
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pci_map);
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pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index);
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memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
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PCI_MEM_SIZE);
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pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
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&s->mmio_bar);
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memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
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PCI_IO_SIZE);
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pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
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/* FIXME: flash aliases to mmio?! */
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memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
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PCI_FLASH_SIZE);
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pci_register_bar_region(&s->dev, 2, 0, &s->flash_bar);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
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assert(s->region1 == 0);
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nic_reset(s);
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