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target-xtensa: implement depbits instruction 

This option provides an instruction for depositing a bit field from the
least significant position of one register to an arbitrary position in
another register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2015-07-12 02:10:17 +03:00
parent 68931a4082
commit 5eeb40c5b1
3 changed files with 26 additions and 0 deletions
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1
target-xtensa/cpu.h
View File

@ -64,6 +64,7 @@ enum {
XTENSA_OPTION_MP_SYNCHRO,
XTENSA_OPTION_CONDITIONAL_STORE,
XTENSA_OPTION_ATOMCTL,
XTENSA_OPTION_DEPBITS,
/* Interrupts and exceptions */
XTENSA_OPTION_EXCEPTION,

5
target-xtensa/overlay_tool.h
View File

@ -30,6 +30,10 @@
{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
#define XTREG_END { .targno = -1 },
#ifndef XCHAL_HAVE_DEPBITS
#define XCHAL_HAVE_DEPBITS 0
#endif
#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif
@ -69,6 +73,7 @@
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
XTENSA_OPTION_ATOMCTL) | \
XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
/* Interrupts and exceptions */ \
XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \

20
target-xtensa/translate.c
View File

@ -1972,6 +1972,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
break;
case 10: /*FP0*/
/*DEPBITS*/
if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
if (!gen_window_check2(dc, RRR_S, RRR_T)) {
break;
}
tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
OP2, RRR_R + 1);
break;
}
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
switch (OP2) {
case 0: /*ADD.Sf*/
@ -2106,6 +2116,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
break;
case 11: /*FP1*/
/*DEPBITS*/
if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
if (!gen_window_check2(dc, RRR_S, RRR_T)) {
break;
}
tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
OP2 + 16, RRR_R + 1);
break;
}
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
#define gen_compare(rel, br, a, b) \