target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el
This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -166,7 +166,7 @@ static off_t sve_fpcr_offset(uint32_t vq)
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static uint32_t sve_current_vq(CPUARMState *env)
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{
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return sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
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return sve_vqm1_for_el(env, arm_current_el(env)) + 1;
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}
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static size_t sve_size_vq(uint32_t vq)
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@ -925,7 +925,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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vfp_get_fpcr(env), vfp_get_fpsr(env));
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if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
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int j, zcr_len = sve_zcr_len_for_el(env, el);
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int j, zcr_len = sve_vqm1_for_el(env, el);
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for (i = 0; i <= FFR_PRED_NUM; i++) {
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bool eol;
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@ -1132,7 +1132,16 @@ void aarch64_sync_64_to_32(CPUARMState *env);
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int fp_exception_el(CPUARMState *env, int cur_el);
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int sve_exception_el(CPUARMState *env, int cur_el);
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uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
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/**
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* sve_vqm1_for_el:
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* @env: CPUARMState
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* @el: exception level
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*
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* Compute the current SVE vector length for @el, in units of
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* Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
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*/
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uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
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static inline bool is_a64(CPUARMState *env)
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{
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@ -152,7 +152,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
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* We report in Vector Granules (VG) which is 64bit in a Z reg
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* while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
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*/
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int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
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int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1;
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return gdb_get_reg64(buf, vq * 2);
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}
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default:
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@ -6215,7 +6215,7 @@ int sve_exception_el(CPUARMState *env, int el)
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/*
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* Given that SVE is enabled, return the vector length for EL.
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*/
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uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
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uint32_t sve_vqm1_for_el(CPUARMState *env, int el)
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{
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ARMCPU *cpu = env_archcpu(env);
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uint32_t len = cpu->sve_max_vq - 1;
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@ -6238,7 +6238,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int cur_el = arm_current_el(env);
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int old_len = sve_zcr_len_for_el(env, cur_el);
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int old_len = sve_vqm1_for_el(env, cur_el);
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int new_len;
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/* Bits other than [3:0] are RAZ/WI. */
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@ -6249,7 +6249,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* Because we arrived here, we know both FP and SVE are enabled;
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* otherwise we would have trapped access to the ZCR_ELn register.
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*/
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new_len = sve_zcr_len_for_el(env, cur_el);
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new_len = sve_vqm1_for_el(env, cur_el);
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if (new_len < old_len) {
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aarch64_sve_narrow_vq(env, new_len + 1);
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}
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@ -11168,7 +11168,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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sve_el = 0;
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}
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} else if (sve_el == 0) {
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DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el));
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DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
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}
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DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
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}
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@ -11534,10 +11534,10 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
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*/
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old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
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old_len = (old_a64 && !sve_exception_el(env, old_el)
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? sve_zcr_len_for_el(env, old_el) : 0);
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? sve_vqm1_for_el(env, old_el) : 0);
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new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
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new_len = (new_a64 && !sve_exception_el(env, new_el)
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? sve_zcr_len_for_el(env, new_el) : 0);
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? sve_vqm1_for_el(env, new_el) : 0);
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/* When changing vector length, clear inaccessible state. */
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if (new_len < old_len) {
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