ETRAX: Add NMI support to the watchdog and the interrupt controller.
* Add NMI and GURU exceptions to teh interrupt controller. * Teach the watchdog timer to signal an NMI before reseting the chip. * Add etraxfs.h to hold api for etrax device models. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4720 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
1b1a38b0aa
commit
5ef98b4742
25
hw/etraxfs.c
25
hw/etraxfs.c
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@ -30,16 +30,7 @@
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#include "devices.h"
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#include "boards.h"
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#include "etraxfs_dma.h"
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/* Init functions for different blocks. */
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extern qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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target_phys_addr_t base);
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void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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qemu_irq *irq, target_phys_addr_t base);
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void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
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target_phys_addr_t base);
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#include "etraxfs.h"
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#define FLASH_SIZE 0x2000000
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#define INTMEM_SIZE (128 * 1024)
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@ -62,7 +53,7 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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qemu_irq *pic;
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struct etraxfs_pic *pic;
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void *etraxfs_dmac;
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struct etraxfs_dma_client *eth[2] = {NULL, NULL};
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int kernel_size;
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@ -110,13 +101,13 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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etraxfs_dmac = etraxfs_dmac_init(env, 0xb0000000, 10);
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for (i = 0; i < 10; i++) {
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/* On ETRAX, odd numbered channels are inputs. */
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etraxfs_dmac_connect(etraxfs_dmac, i, pic + 7 + i, i & 1);
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etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1);
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}
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/* Add the two ethernet blocks. */
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eth[0] = etraxfs_eth_init(&nd_table[0], env, pic + 25, 0xb0034000);
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eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0xb0034000);
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if (nb_nics > 1)
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eth[1] = etraxfs_eth_init(&nd_table[1], env, pic + 26, 0xb0036000);
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eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0xb0036000);
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/* The DMA Connector block is missing, hardwire things for now. */
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etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
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@ -127,12 +118,12 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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}
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/* 2 timers. */
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etraxfs_timer_init(env, pic + 0x1b, 0xb001e000);
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etraxfs_timer_init(env, pic + 0x1b, 0xb005e000);
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etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb001e000);
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etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb005e000);
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for (i = 0; i < 4; i++) {
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if (serial_hds[i]) {
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etraxfs_ser_init(env, pic + 0x14 + i,
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etraxfs_ser_init(env, pic->irq + 0x14 + i,
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serial_hds[i], 0xb0026000 + i * 0x2000);
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}
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}
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@ -0,0 +1,42 @@
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/*
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* QEMU ETRAX System Emulator
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "etraxfs_dma.h"
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struct etraxfs_pic
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{
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qemu_irq *irq;
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qemu_irq *nmi;
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qemu_irq *guru;
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void *internal;
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};
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struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
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target_phys_addr_t base);
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void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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qemu_irq *irq, target_phys_addr_t base);
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void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
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target_phys_addr_t base);
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@ -24,6 +24,7 @@
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#include <stdio.h>
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#include "hw.h"
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#include "etraxfs.h"
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#define D(x)
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@ -143,7 +144,7 @@ void irq_info(void)
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{
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}
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static void etraxfs_pic_handler(void *opaque, int irq, int level)
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static void irq_handler(void *opaque, int irq, int level)
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{
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struct fs_pic_state_t *fs = (void *)opaque;
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CPUState *env = fs->env;
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@ -187,22 +188,56 @@ static void etraxfs_pic_handler(void *opaque, int irq, int level)
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}
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}
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qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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static void nmi_handler(void *opaque, int irq, int level)
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{
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struct fs_pic_state_t *fs = (void *)opaque;
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CPUState *env = fs->env;
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uint32_t mask;
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mask = 1 << irq;
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if (level)
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fs->r_nmi |= mask;
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else
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fs->r_nmi &= ~mask;
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if (fs->r_nmi)
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
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}
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static void guru_handler(void *opaque, int irq, int level)
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{
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struct fs_pic_state_t *fs = (void *)opaque;
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CPUState *env = fs->env;
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cpu_abort(env, "%s unsupported exception\n", __func__);
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}
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struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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{
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struct fs_pic_state_t *fs;
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qemu_irq *pic;
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struct fs_pic_state_t *fs = NULL;
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struct etraxfs_pic *pic = NULL;
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int intr_vect_regs;
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fs = qemu_mallocz(sizeof *fs);
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if (!fs)
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return NULL;
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fs->env = env;
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pic = qemu_mallocz(sizeof *pic);
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pic->internal = fs = qemu_mallocz(sizeof *fs);
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if (!fs || !pic)
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goto err;
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pic = qemu_allocate_irqs(etraxfs_pic_handler, fs, 30);
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fs->env = env;
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pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
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pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
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pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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cpu_register_physical_memory(base, 0x14, intr_vect_regs);
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fs->base = base;
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return pic;
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err:
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free(pic);
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free(fs);
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return NULL;
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}
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@ -46,6 +46,7 @@
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struct fs_timer_t {
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CPUState *env;
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qemu_irq *irq;
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qemu_irq *nmi;
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target_phys_addr_t base;
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QEMUBH *bh_t0;
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@ -56,6 +57,8 @@ struct fs_timer_t {
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ptimer_state *ptimer_wd;
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struct timeval last;
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int wd_hits;
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/* Control registers. */
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uint32_t rw_tmr0_div;
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uint32_t r_tmr0_data;
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@ -129,6 +132,7 @@ static void update_ctrl(struct fs_timer_t *t, int tnum)
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unsigned int freq_hz;
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unsigned int div;
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uint32_t ctrl;
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ptimer_state *timer;
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if (tnum == 0) {
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@ -163,8 +167,8 @@ static void update_ctrl(struct fs_timer_t *t, int tnum)
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D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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div = div * TIMER_SLOWDOWN;
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div >>= 15;
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freq_hz >>= 15;
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div >>= 10;
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freq_hz >>= 10;
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ptimer_set_freq(timer, freq_hz);
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ptimer_set_limit(timer, div, 0);
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@ -216,7 +220,18 @@ static void timer1_hit(void *opaque)
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static void watchdog_hit(void *opaque)
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{
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qemu_system_reset_request();
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struct fs_timer_t *t = opaque;
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if (t->wd_hits == 0) {
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/* real hw gives a single tick before reseting but we are
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a bit friendlier to compensate for our slower execution. */
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ptimer_set_count(t->ptimer_wd, 10);
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ptimer_run(t->ptimer_wd, 1);
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qemu_irq_raise(t->nmi[0]);
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}
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else
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qemu_system_reset_request();
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t->wd_hits++;
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}
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static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
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@ -237,6 +252,11 @@ static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
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D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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wd_en, new_key, wd_key, new_cmd, wd_cnt));
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if (t->wd_hits)
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qemu_irq_lower(t->nmi[0]);
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t->wd_hits = 0;
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ptimer_set_freq(t->ptimer_wd, 760);
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if (wd_cnt == 0)
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wd_cnt = 256;
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@ -320,7 +340,7 @@ static void etraxfs_timer_reset(void *opaque)
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qemu_irq_lower(t->irq[0]);
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}
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
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target_phys_addr_t base)
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{
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static struct fs_timer_t *t;
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@ -337,6 +357,7 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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t->ptimer_t1 = ptimer_init(t->bh_t1);
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t->ptimer_wd = ptimer_init(t->bh_wd);
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t->irq = irqs;
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t->nmi = nmi;
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t->env = env;
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t->base = base;
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