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target-ppc: add maddhd and maddhdu instruction 

maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned

Above two instruction are dual form and differ by 1 bit
(31st bit)

Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the higher dword in the target
register(RT).

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2016-07-26 17:28:37 +05:30 committed by David Gibson
parent aeeb044c7b
commit 5f29cc8292
1 changed files with 25 additions and 0 deletions
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25
target-ppc/translate.c
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@ -7749,6 +7749,29 @@ static void gen_maddld(DisasContext *ctx)
tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
tcg_temp_free_i64(t1);
}
/* maddhd maddhdu */
static void gen_maddhd_maddhdu(DisasContext *ctx)
{
TCGv_i64 lo = tcg_temp_new_i64();
TCGv_i64 hi = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
if (Rc(ctx->opcode)) {
tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rB(ctx->opcode)]);
tcg_gen_movi_i64(t1, 0);
} else {
tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rB(ctx->opcode)]);
tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
}
tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
cpu_gpr[rC(ctx->opcode)], t1);
tcg_temp_free_i64(lo);
tcg_temp_free_i64(hi);
tcg_temp_free_i64(t1);
}
#endif /* defined(TARGET_PPC64) */
GEN_VXFORM_NOA(vclzb, 1, 28)
@ -10367,6 +10390,8 @@ GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
PPC2_ISA300),
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),