target-tricore: Several translator and cpu model fixes
Fix tc1796 cpu model using wrong ISA version. Fix cond_add sometimes writing back wrong result. Fix RCR_SEL and RCR_SELN using wrong registers for result and cond. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -118,7 +118,7 @@ static void tc1796_initfn(Object *obj)
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{
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TriCoreCPU *cpu = TRICORE_CPU(obj);
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set_feature(&cpu->env, TRICORE_FEATURE_13);
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set_feature(&cpu->env, TRICORE_FEATURE_131);
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}
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static void aurix_initfn(Object *obj)
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@ -255,6 +255,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 * t2;
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return suov32(env, result);
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}
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@ -745,7 +745,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
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tcg_gen_and_tl(temp, temp, mask);
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tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
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/* write back result */
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tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
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tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
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tcg_temp_free(t0);
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tcg_temp_free(temp);
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@ -3898,7 +3898,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
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case OPC2_32_RCR_SEL:
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temp = tcg_const_i32(0);
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temp2 = tcg_const_i32(const9);
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
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cpu_gpr_d[r1], temp2);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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@ -3906,7 +3906,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
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case OPC2_32_RCR_SELN:
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temp = tcg_const_i32(0);
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temp2 = tcg_const_i32(const9);
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
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cpu_gpr_d[r1], temp2);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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