Compile pflash_cfi02 only once
Push TARGET_WORDS_BIGENDIAN dependency to board level. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
53b67b3052
commit
5f9fc5ad7e
@ -135,6 +135,7 @@ hw-obj-y += watchdog.o
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hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
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hw-obj-$(CONFIG_ECC) += ecc.o
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hw-obj-$(CONFIG_NAND) += nand.o
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hw-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
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hw-obj-$(CONFIG_M48T59) += m48t59.o
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hw-obj-$(CONFIG_ESCC) += escc.o
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@ -202,7 +202,7 @@ obj-ppc-y += heathrow_pic.o grackle_pci.o ppc_oldworld.o
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# NewWorld PowerMac
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obj-ppc-y += unin_pci.o ppc_newworld.o dec_pci.o
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# PowerPC 4xx boards
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obj-ppc-y += pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc440.o ppc440_bamboo.o
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# PowerPC E500 boards
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obj-ppc-y += ppce500_pci.o ppce500_mpc8544ds.o
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@ -239,8 +239,6 @@ obj-cris-y += etraxfs_eth.o
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obj-cris-y += etraxfs_timer.o
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obj-cris-y += etraxfs_ser.o
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obj-cris-y += pflash_cfi02.o
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ifeq ($(TARGET_ARCH), sparc64)
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obj-sparc-y = sun4u.o pckbd.o apb_pci.o
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obj-sparc-y += vga.o
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@ -268,7 +266,7 @@ obj-arm-y += omap2.o omap_dss.o soc_dma.o
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obj-arm-y += omap_sx1.o palm.o tsc210x.o
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obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
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obj-arm-y += mst_fpga.o mainstone.o
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obj-arm-y += musicpal.o pflash_cfi02.o bitbang_i2c.o marvell_88w8618_audio.o
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obj-arm-y += musicpal.o bitbang_i2c.o marvell_88w8618_audio.o
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obj-arm-y += framebuffer.o
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obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
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obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
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@ -26,3 +26,4 @@ CONFIG_LAN9118=y
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CONFIG_SMC91C111=y
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CONFIG_DS1338=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI02=y
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@ -3,3 +3,4 @@
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CONFIG_NAND=y
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CONFIG_PTIMER=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI02=y
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@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI02=y
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@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI02=y
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@ -17,3 +17,4 @@ CONFIG_IDE_CMD646=y
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CONFIG_NE2000_ISA=y
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CONFIG_SOUND=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_PFLASH_CFI02=y
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@ -92,7 +92,7 @@ void bareetraxfs_init (ram_addr_t ram_size,
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dinfo ? dinfo->bdrv : NULL, (64 * 1024),
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FLASH_SIZE >> 16,
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1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
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0x555, 0x2aa);
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0x555, 0x2aa, 0);
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cpu_irq = cris_pic_init_cpu(env);
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dev = qdev_create(NULL, "etraxfs,pic");
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/* FIXME: Is there a proper way to signal vectors to the CPU core? */
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@ -14,7 +14,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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int nb_blocs, int nb_mappings, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0, uint16_t unlock_addr1);
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uint16_t unlock_addr0, uint16_t unlock_addr1,
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int be);
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/* nand.c */
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typedef struct NANDFlashState NANDFlashState;
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@ -1558,12 +1558,22 @@ static void musicpal_init(ram_addr_t ram_size,
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* 0xFF800000 (if there is 8 MB flash). So remap flash access if the
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* image is smaller than 32 MB.
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*/
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#ifdef TARGET_WORDS_BIGENDIAN
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pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
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dinfo->bdrv, 0x10000,
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(flash_size + 0xffff) >> 16,
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MP_FLASH_SIZE_MAX / flash_size,
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2, 0x00BF, 0x236D, 0x0000, 0x0000,
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0x5555, 0x2AAA);
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0x5555, 0x2AAA, 1);
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#else
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pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
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dinfo->bdrv, 0x10000,
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(flash_size + 0xffff) >> 16,
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MP_FLASH_SIZE_MAX / flash_size,
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2, 0x00BF, 0x236D, 0x0000, 0x0000,
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0x5555, 0x2AAA, 0);
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#endif
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}
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sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
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@ -103,7 +103,8 @@ static void pflash_timer (void *opaque)
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pfl->cmd = 0;
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}
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width)
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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int width, int be)
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{
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target_phys_addr_t boff;
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uint32_t ret;
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@ -140,27 +141,27 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, int width
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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#endif
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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}
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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#else
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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#endif
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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}
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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}
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@ -223,7 +224,7 @@ static void pflash_update(pflash_t *pfl, int offset,
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}
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static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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uint32_t value, int width)
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uint32_t value, int width, int be)
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{
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target_phys_addr_t boff;
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uint8_t *p;
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@ -316,27 +317,27 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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pflash_update(pfl, offset, 1);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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p[offset] &= value >> 8;
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p[offset + 1] &= value;
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#else
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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#endif
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if (be) {
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p[offset] &= value >> 8;
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p[offset + 1] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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}
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pflash_update(pfl, offset, 2);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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p[offset] &= value >> 24;
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p[offset + 1] &= value >> 16;
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p[offset + 2] &= value >> 8;
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p[offset + 3] &= value;
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#else
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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p[offset + 2] &= value >> 16;
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p[offset + 3] &= value >> 24;
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#endif
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if (be) {
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p[offset] &= value >> 24;
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p[offset + 1] &= value >> 16;
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p[offset + 2] &= value >> 8;
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p[offset + 3] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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p[offset + 2] &= value >> 16;
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p[offset + 3] &= value >> 24;
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}
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pflash_update(pfl, offset, 4);
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break;
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}
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@ -451,57 +452,110 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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}
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static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1);
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return pflash_read(opaque, addr, 1, 1);
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}
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static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1, 0);
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}
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static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 2);
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return pflash_read(pfl, addr, 2, 1);
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}
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static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 4);
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return pflash_read(pfl, addr, 2, 0);
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}
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static void pflash_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1);
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}
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static void pflash_writew (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2);
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return pflash_read(pfl, addr, 4, 1);
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}
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static void pflash_writel (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4);
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return pflash_read(pfl, addr, 4, 0);
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}
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static CPUWriteMemoryFunc * const pflash_write_ops[] = {
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&pflash_writeb,
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&pflash_writew,
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&pflash_writel,
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static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 1);
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}
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static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 0);
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}
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static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 1);
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}
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static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 0);
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}
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static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 1);
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}
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static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 0);
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}
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static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
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&pflash_writeb_be,
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&pflash_writew_be,
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&pflash_writel_be,
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};
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static CPUReadMemoryFunc * const pflash_read_ops[] = {
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&pflash_readb,
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&pflash_readw,
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&pflash_readl,
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static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
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&pflash_readb_be,
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&pflash_readw_be,
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&pflash_readl_be,
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};
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static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
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&pflash_writeb_le,
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&pflash_writew_le,
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&pflash_writel_le,
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};
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static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
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&pflash_readb_le,
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&pflash_readw_le,
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&pflash_readl_le,
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};
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/* Count trailing zeroes of a 32 bits quantity */
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@ -543,7 +597,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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int nb_blocs, int nb_mappings, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3,
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uint16_t unlock_addr0, uint16_t unlock_addr1)
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uint16_t unlock_addr0, uint16_t unlock_addr1,
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int be)
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{
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pflash_t *pfl;
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int32_t chip_len;
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@ -559,8 +614,15 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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pfl = qemu_mallocz(sizeof(pflash_t));
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/* FIXME: Allocate ram ourselves. */
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pfl->storage = qemu_get_ram_ptr(off);
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops,
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pfl);
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if (be) {
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
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pflash_write_ops_be,
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pfl);
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} else {
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
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pflash_write_ops_le,
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pfl);
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}
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pfl->off = off;
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pfl->base = base;
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pfl->chip_len = chip_len;
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@ -228,7 +228,8 @@ static void ref405ep_init (ram_addr_t ram_size,
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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dinfo->bdrv, 65536, fl_sectors, 1,
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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fl_idx++;
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} else
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#endif
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@ -542,7 +543,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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dinfo->bdrv, 65536, fl_sectors, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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fl_idx++;
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} else
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#endif
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@ -584,7 +586,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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bios_offset = qemu_ram_alloc(bios_size);
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pflash_cfi02_register(0xfc000000, bios_offset,
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dinfo->bdrv, 65536, fl_sectors, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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fl_idx++;
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}
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/* Register CLPD & LCD display */
|
||||
|
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Reference in New Issue
Block a user