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accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus() 

Forward tlb_flush_page_bits_by_mmuidx_all_cpus to
tlb_flush_range_by_mmuidx_all_cpus passing TARGET_PAGE_SIZE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-6-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-09 17:16:14 +02:00 committed by Peter Maydell
parent e5b1921bd4
commit 600b819f23
2 changed files with 30 additions and 7 deletions
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24
accel/tcg/cputlb.c
View File

@ -839,16 +839,18 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits);
} }
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
target_ulong addr, target_ulong addr, target_ulong len,
uint16_t idxmap, uint16_t idxmap, unsigned bits)
unsigned bits)
{ {
TLBFlushRangeData d; TLBFlushRangeData d;
CPUState *dst_cpu; CPUState *dst_cpu;
/* If all bits are significant, this devolves to tlb_flush_page. */ /*
if (bits >= TARGET_LONG_BITS) { * If all bits are significant, and len is small,
* this devolves to tlb_flush_page.
*/
if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
return; return;
} }
@ -860,7 +862,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
/* This should already be page aligned */ /* This should already be page aligned */
d.addr = addr & TARGET_PAGE_MASK; d.addr = addr & TARGET_PAGE_MASK;
d.len = TARGET_PAGE_SIZE; d.len = len;
d.idxmap = idxmap; d.idxmap = idxmap;
d.bits = bits; d.bits = bits;
@ -877,6 +879,14 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d); tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d);
} }
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
target_ulong addr,
uint16_t idxmap, unsigned bits)
{
tlb_flush_range_by_mmuidx_all_cpus(src_cpu, addr, TARGET_PAGE_SIZE,
idxmap, bits);
}
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
target_ulong addr, target_ulong addr,
uint16_t idxmap, uint16_t idxmap,

13
include/exec/exec-all.h
View File

@ -276,6 +276,12 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
target_ulong len, uint16_t idxmap, target_ulong len, uint16_t idxmap,
unsigned bits); unsigned bits);
/* Similarly, with broadcast and syncing. */
void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
target_ulong len, uint16_t idxmap,
unsigned bits);
/** /**
* tlb_set_page_with_attrs: * tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for * @cpu: CPU to add this TLB entry for
@ -384,6 +390,13 @@ static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
unsigned bits) unsigned bits)
{ {
} }
static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
target_ulong addr,
target_ulong len,
uint16_t idxmap,
unsigned bits)
{
}
#endif #endif
/** /**
* probe_access: * probe_access: