vfio/pci: Cleanup Nvidia 0x3d0 quirk
The Nvidia 0x3d0 quirk makes use of a two separate registers and gives us our first chance to make use of separate memory regions for each to simplify the code a bit. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Alex Williamson
parent
b946d28611
commit
6029a424be
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@ -390,76 +390,121 @@ static void vfio_probe_ati_bar2_4000_quirk(VFIOPCIDevice *vdev, int nr)
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* through 0x3d0. This quirk doesn't seem to be necessary on newer cards
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* that use the I/O port BAR5 window but it doesn't hurt to leave it.
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*/
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enum {
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NV_3D0_NONE = 0,
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NV_3D0_SELECT,
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NV_3D0_WINDOW,
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NV_3D0_READ,
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NV_3D0_WRITE,
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typedef enum {NONE = 0, SELECT, WINDOW, READ, WRITE} VFIONvidia3d0State;
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static const char *nv3d0_states[] = { "NONE", "SELECT",
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"WINDOW", "READ", "WRITE" };
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typedef struct VFIONvidia3d0Quirk {
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VFIOPCIDevice *vdev;
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VFIONvidia3d0State state;
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uint32_t offset;
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} VFIONvidia3d0Quirk;
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static uint64_t vfio_nvidia_3d4_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIONvidia3d0Quirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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quirk->state = NONE;
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return vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
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addr + 0x14, size);
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}
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static void vfio_nvidia_3d4_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIONvidia3d0Quirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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VFIONvidia3d0State old_state = quirk->state;
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quirk->state = NONE;
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switch (data) {
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case 0x338:
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if (old_state == NONE) {
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quirk->state = SELECT;
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trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
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nv3d0_states[quirk->state]);
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}
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break;
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case 0x538:
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if (old_state == WINDOW) {
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quirk->state = READ;
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trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
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nv3d0_states[quirk->state]);
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}
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break;
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case 0x738:
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if (old_state == WINDOW) {
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quirk->state = WRITE;
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trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
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nv3d0_states[quirk->state]);
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}
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break;
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}
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vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
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addr + 0x14, data, size);
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}
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static const MemoryRegionOps vfio_nvidia_3d4_quirk = {
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.read = vfio_nvidia_3d4_quirk_read,
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.write = vfio_nvidia_3d4_quirk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOLegacyQuirk *quirk = opaque;
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VFIONvidia3d0Quirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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PCIDevice *pdev = &vdev->pdev;
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VFIONvidia3d0State old_state = quirk->state;
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uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
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addr + quirk->data.base_offset, size);
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addr + 0x10, size);
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if (quirk->data.flags == NV_3D0_READ && addr == quirk->data.data_offset) {
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data = vfio_pci_read_config(pdev, quirk->data.address_val, size);
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trace_vfio_nvidia_3d0_quirk_read(size, data);
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quirk->state = NONE;
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if (old_state == READ &&
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(quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) {
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uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1);
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data = vfio_pci_read_config(&vdev->pdev, offset, size);
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trace_vfio_quirk_nvidia_3d0_read(vdev->vbasedev.name,
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offset, size, data);
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}
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quirk->data.flags = NV_3D0_NONE;
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return data;
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}
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static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOLegacyQuirk *quirk = opaque;
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VFIONvidia3d0Quirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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PCIDevice *pdev = &vdev->pdev;
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VFIONvidia3d0State old_state = quirk->state;
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switch (quirk->data.flags) {
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case NV_3D0_NONE:
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if (addr == quirk->data.address_offset && data == 0x338) {
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quirk->data.flags = NV_3D0_SELECT;
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}
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break;
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case NV_3D0_SELECT:
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quirk->data.flags = NV_3D0_NONE;
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if (addr == quirk->data.data_offset &&
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(data & ~quirk->data.address_mask) == quirk->data.address_match) {
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quirk->data.flags = NV_3D0_WINDOW;
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quirk->data.address_val = data & quirk->data.address_mask;
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}
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break;
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case NV_3D0_WINDOW:
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quirk->data.flags = NV_3D0_NONE;
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if (addr == quirk->data.address_offset) {
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if (data == 0x538) {
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quirk->data.flags = NV_3D0_READ;
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} else if (data == 0x738) {
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quirk->data.flags = NV_3D0_WRITE;
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}
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}
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break;
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case NV_3D0_WRITE:
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quirk->data.flags = NV_3D0_NONE;
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if (addr == quirk->data.data_offset) {
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vfio_pci_write_config(pdev, quirk->data.address_val, data, size);
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trace_vfio_nvidia_3d0_quirk_write(data, size);
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quirk->state = NONE;
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if (old_state == SELECT) {
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quirk->offset = (uint32_t)data;
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quirk->state = WINDOW;
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trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
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nv3d0_states[quirk->state]);
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} else if (old_state == WRITE) {
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if ((quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) {
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uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1);
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vfio_pci_write_config(&vdev->pdev, offset, data, size);
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trace_vfio_quirk_nvidia_3d0_write(vdev->vbasedev.name,
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offset, data, size);
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return;
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}
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break;
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}
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vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
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addr + quirk->data.base_offset, data, size);
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addr + 0x10, data, size);
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}
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static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
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@ -470,37 +515,34 @@ static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
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static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice *vdev)
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{
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PCIDevice *pdev = &vdev->pdev;
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VFIOQuirk *quirk;
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VFIOLegacyQuirk *legacy;
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VFIONvidia3d0Quirk *data;
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if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA ||
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if (!vfio_pci_is(vdev, PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID) ||
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!vdev->bars[1].region.size) {
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return;
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}
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quirk = g_malloc0(sizeof(*quirk));
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quirk->data = legacy = g_malloc0(sizeof(*legacy));
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quirk->mem = legacy->mem = g_malloc0_n(sizeof(MemoryRegion), 1);
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quirk->nr_mem = 1;
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legacy->vdev = vdev;
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legacy->data.base_offset = 0x10;
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legacy->data.address_offset = 4;
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legacy->data.address_size = 2;
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legacy->data.address_match = 0x1800;
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legacy->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
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legacy->data.data_offset = 0;
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legacy->data.data_size = 4;
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quirk->data = data = g_malloc0(sizeof(*data));
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quirk->mem = g_malloc0_n(sizeof(MemoryRegion), 2);
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quirk->nr_mem = 2;
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data->vdev = vdev;
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memory_region_init_io(quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk,
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legacy, "vfio-nvidia-3d0-quirk", 6);
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memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_nvidia_3d4_quirk,
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data, "vfio-nvidia-3d4-quirk", 2);
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memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
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legacy->data.base_offset, quirk->mem);
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0x14 /* 0x3c0 + 0x14 */, &quirk->mem[0]);
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memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_nvidia_3d0_quirk,
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data, "vfio-nvidia-3d0-quirk", 2);
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memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
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0x10 /* 0x3c0 + 0x10 */, &quirk->mem[1]);
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QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
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quirk, next);
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trace_vfio_vga_probe_nvidia_3d0_quirk(vdev->vbasedev.name);
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trace_vfio_quirk_nvidia_3d0_probe(vdev->vbasedev.name);
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}
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/*
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@ -1557,9 +1557,6 @@ vfio_rtl8168_quirk_write(const char *name, uint64_t val) "%s [address]: 0x%"PRIx
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vfio_rtl8168_quirk_msix(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64
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vfio_rtl8168_quirk_enable(const char *name) "%s"
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vfio_probe_ati_bar2_4000_quirk(const char *name) "Enabled ATI/AMD BAR2 0x4000 quirk for device %s"
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vfio_nvidia_3d0_quirk_read(int size, uint64_t data) " (0x3d0, %d) = 0x%"PRIx64
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vfio_nvidia_3d0_quirk_write(uint64_t data, int size) " (0x3d0, 0x%"PRIx64", %d)"
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vfio_vga_probe_nvidia_3d0_quirk(const char *name) "Enabled NVIDIA VGA 0x3d0 quirk for device %s"
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vfio_probe_nvidia_bar5_window_quirk(const char *name) "Enabled NVIDIA BAR5 window quirk for device %s"
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vfio_probe_nvidia_bar0_88000_quirk(const char *name) "Enabled NVIDIA BAR0 0x88000 quirk for device %s"
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vfio_probe_nvidia_bar0_1800_quirk_id(int id) "Nvidia NV%02x"
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@ -1587,6 +1584,10 @@ vfio_pci_reset_pm(const char *name) "%s PCI PM Reset"
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vfio_quirk_rom_blacklisted(const char *name, uint16_t vid, uint16_t did) "%s %04x:%04x"
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vfio_quirk_ati_3c3_read(const char *name, uint64_t data) "%s 0x%"PRIx64
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vfio_quirk_ati_3c3_probe(const char *name) "%s"
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vfio_quirk_nvidia_3d0_state(const char *name, const char *state) "%s %s"
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vfio_quirk_nvidia_3d0_read(const char *name, uint8_t offset, unsigned size, uint64_t val) " (%s, @0x%x, len=0x%x) %"PRIx64
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vfio_quirk_nvidia_3d0_write(const char *name, uint8_t offset, uint64_t data, unsigned size) "(%s, @0x%x, 0x%"PRIx64", len=0x%x)"
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vfio_quirk_nvidia_3d0_probe(const char *name) "%s"
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# hw/vfio/vfio-common.c
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vfio_region_write(const char *name, int index, uint64_t addr, uint64_t data, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)"
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