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target/loongarch: Drop temp_new 

Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-24 19:05:39 -10:00
parent af1872380d
commit 60a7e25ea2
3 changed files with 4 additions and 22 deletions
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2
target/loongarch/insn_trans/trans_privileged.c.inc
View File

@ -243,7 +243,7 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
dest = gpr_dst(ctx, a->rd, EXT_NONE); dest = gpr_dst(ctx, a->rd, EXT_NONE);
csr->writefn(dest, cpu_env, src1); csr->writefn(dest, cpu_env, src1);
} else { } else {
dest = temp_new(ctx); dest = tcg_temp_new();
tcg_gen_ld_tl(dest, cpu_env, csr->offset); tcg_gen_ld_tl(dest, cpu_env, csr->offset);
tcg_gen_st_tl(src1, cpu_env, csr->offset); tcg_gen_st_tl(src1, cpu_env, csr->offset);
} }

21
target/loongarch/translate.c
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@ -85,9 +85,6 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound); ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->zero = tcg_constant_tl(0); ctx->zero = tcg_constant_tl(0);
} }
@ -110,12 +107,6 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
* *
* Further, we may provide an extension for word operations. * Further, we may provide an extension for word operations.
*/ */
static TCGv temp_new(DisasContext *ctx)
{
assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
return ctx->temp[ctx->ntemp++] = tcg_temp_new();
}
static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext) static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
{ {
TCGv t; TCGv t;
@ -128,11 +119,11 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
case EXT_NONE: case EXT_NONE:
return cpu_gpr[reg_num]; return cpu_gpr[reg_num];
case EXT_SIGN: case EXT_SIGN:
t = temp_new(ctx); t = tcg_temp_new();
tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
return t; return t;
case EXT_ZERO: case EXT_ZERO:
t = temp_new(ctx); t = tcg_temp_new();
tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
return t; return t;
} }
@ -142,7 +133,7 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext) static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
{ {
if (reg_num == 0 || dst_ext) { if (reg_num == 0 || dst_ext) {
return temp_new(ctx); return tcg_temp_new();
} }
return cpu_gpr[reg_num]; return cpu_gpr[reg_num];
} }
@ -195,12 +186,6 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
generate_exception(ctx, EXCCODE_INE); generate_exception(ctx, EXCCODE_INE);
} }
for (int i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
ctx->temp[i] = NULL;
}
ctx->ntemp = 0;
ctx->base.pc_next += 4; ctx->base.pc_next += 4;
} }

3
target/loongarch/translate.h
View File

@ -32,9 +32,6 @@ typedef struct DisasContext {
uint16_t mem_idx; uint16_t mem_idx;
uint16_t plv; uint16_t plv;
TCGv zero; TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
uint8_t ntemp;
} DisasContext; } DisasContext;
void generate_exception(DisasContext *ctx, int excp); void generate_exception(DisasContext *ctx, int excp);