omap1: convert to memory API (part IV)
Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Avi Kivity <avi@redhat.com>
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a4ebbd18b1
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@ -841,6 +841,7 @@ struct omap_mpu_state_s {
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MemoryRegion clkdsp_iomem;
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MemoryRegion pwl_iomem;
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MemoryRegion pwt_iomem;
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MemoryRegion mpui_io_iomem;
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struct omap_dma_port_if_s {
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uint32_t (*read[3])(struct omap_mpu_state_s *s,
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87
hw/omap1.c
87
hw/omap1.c
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@ -3452,6 +3452,7 @@ void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
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/* LED Pulse Generators */
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struct omap_lpg_s {
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MemoryRegion iomem;
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QEMUTimer *tm;
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uint8_t control;
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@ -3516,11 +3517,16 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
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omap_lpg_update(s);
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}
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static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
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static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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if (size != 1) {
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return omap_badwidth_read8(opaque, addr);
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}
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switch (offset) {
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case 0x00: /* LCR */
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return s->control;
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@ -3534,11 +3540,15 @@ static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
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}
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static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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if (size != 1) {
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return omap_badwidth_write8(opaque, addr, value);
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}
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switch (offset) {
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case 0x00: /* LCR */
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if (~value & (1 << 6)) /* LPGRES */
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@ -3558,16 +3568,10 @@ static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
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omap_lpg_read,
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omap_badwidth_read8,
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omap_badwidth_read8,
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};
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static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
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omap_lpg_write,
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omap_badwidth_write8,
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omap_badwidth_write8,
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static const MemoryRegionOps omap_lpg_ops = {
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.read = omap_lpg_read,
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.write = omap_lpg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void omap_lpg_clk_update(void *opaque, int line, int on)
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@ -3578,9 +3582,9 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
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omap_lpg_update(s);
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}
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static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
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static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
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target_phys_addr_t base, omap_clk clk)
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{
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int iomemtype;
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struct omap_lpg_s *s = (struct omap_lpg_s *)
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g_malloc0(sizeof(struct omap_lpg_s));
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@ -3588,9 +3592,8 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
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omap_lpg_reset(s);
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iomemtype = cpu_register_io_memory(omap_lpg_readfn,
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omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x800, iomemtype);
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memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
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memory_region_add_subregion(system_memory, base, &s->iomem);
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omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
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@ -3598,8 +3601,13 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
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}
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/* MPUI Peripheral Bridge configuration */
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static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
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static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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if (size != 2) {
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return omap_badwidth_read16(opaque, addr);
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}
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if (addr == OMAP_MPUI_BASE) /* CMR */
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return 0xfe4d;
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@ -3607,23 +3615,26 @@ static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
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return 0;
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}
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static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
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omap_badwidth_read16,
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omap_mpui_io_read,
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omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
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omap_badwidth_write16,
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omap_badwidth_write16,
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omap_badwidth_write16,
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};
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static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
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static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
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omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
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/* FIXME: infinite loop */
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omap_badwidth_write16(opaque, addr, value);
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}
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static const MemoryRegionOps omap_mpui_io_ops = {
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.read = omap_mpui_io_read,
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.write = omap_mpui_io_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void omap_setup_mpui_io(MemoryRegion *system_memory,
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struct omap_mpu_state_s *mpu)
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{
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memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
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"omap-mpui-io", 0x7fff);
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memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
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&mpu->mpui_io_iomem);
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}
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/* General chip reset */
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@ -3947,8 +3958,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
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0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
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&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
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s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
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s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
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s->led[0] = omap_lpg_init(system_memory,
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0xfffbd000, omap_findclk(s, "clk32-kHz"));
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s->led[1] = omap_lpg_init(system_memory,
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0xfffbd800, omap_findclk(s, "clk32-kHz"));
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/* Register mappings not currenlty implemented:
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* MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
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@ -3966,7 +3979,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
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*/
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omap_setup_dsp_mapping(omap15xx_dsp_mm);
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omap_setup_mpui_io(s);
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omap_setup_mpui_io(system_memory, s);
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qemu_register_reset(omap1_mpu_reset, s);
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