target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an implementation based on the helper, with the main difference being changing the -1 (aka all bits set to 1) result returned by cmp when true to +1. It also implemented a .fni4 version of those instructions and dropped the helper. vaddcuw: rept loop master patch 8 12500 0,01008200 0,00612400 (-39.3%) 25 4000 0,01091500 0,00471600 (-56.8%) 100 1000 0,01332500 0,00593700 (-55.4%) 500 200 0,01998500 0,01275700 (-36.2%) 2500 40 0,04704300 0,04364300 (-7.2%) 8000 12 0,10748200 0,11241000 (+4.6%) vsubcuw: rept loop master patch 8 12500 0,01226200 0,00571600 (-53.4%) 25 4000 0,01493500 0,00462100 (-69.1%) 100 1000 0,01522700 0,00455100 (-70.1%) 500 200 0,02384600 0,01133500 (-52.5%) 2500 40 0,04935200 0,03178100 (-35.6%) 8000 12 0,09039900 0,09440600 (+4.4%) Overall there was a gain in performance, but the TCGop code was still slightly bigger in the new version (it went from 4 to 5). Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221019125040.48028-4-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
306e475335
commit
611bc69bf6
@ -193,11 +193,9 @@ DEF_HELPER_FLAGS_3(vslo, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vsro, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vsrv, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vslv, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vaddcuw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_2(vprtybw, TCG_CALL_NO_RWG, void, avr, avr)
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DEF_HELPER_FLAGS_2(vprtybd, TCG_CALL_NO_RWG, void, avr, avr)
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DEF_HELPER_FLAGS_2(vprtybq, TCG_CALL_NO_RWG, void, avr, avr)
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DEF_HELPER_FLAGS_3(vsubcuw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_5(vaddsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_5(vaddshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
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DEF_HELPER_FLAGS_5(vaddsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
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@ -608,12 +608,14 @@ VRLQNM 000100 ..... ..... ..... 00101000101 @VX
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## Vector Integer Arithmetic Instructions
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VADDCUW 000100 ..... ..... ..... 00110000000 @VX
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VADDCUQ 000100 ..... ..... ..... 00101000000 @VX
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VADDUQM 000100 ..... ..... ..... 00100000000 @VX
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VADDEUQM 000100 ..... ..... ..... ..... 111100 @VA
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VADDECUQ 000100 ..... ..... ..... ..... 111101 @VA
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VSUBCUW 000100 ..... ..... ..... 10110000000 @VX
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VSUBCUQ 000100 ..... ..... ..... 10101000000 @VX
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VSUBUQM 000100 ..... ..... ..... 10100000000 @VX
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@ -492,15 +492,6 @@ static inline void set_vscr_sat(CPUPPCState *env)
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env->vscr_sat.u32[0] = 1;
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}
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void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
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r->u32[i] = ~a->u32[i] < b->u32[i];
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}
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}
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/* vprtybw */
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void helper_vprtybw(ppc_avr_t *r, ppc_avr_t *b)
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{
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@ -1962,15 +1953,6 @@ void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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#endif
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}
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void helper_vsubcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
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r->u32[i] = a->u32[i] >= b->u32[i];
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}
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}
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void helper_vsumsws(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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int64_t t;
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@ -803,8 +803,6 @@ GEN_VXFORM(vsrv, 2, 28);
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GEN_VXFORM(vslv, 2, 29);
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GEN_VXFORM(vslo, 6, 16);
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GEN_VXFORM(vsro, 6, 17);
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GEN_VXFORM(vaddcuw, 0, 6);
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GEN_VXFORM(vsubcuw, 0, 22);
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static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
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void (*gen_gvec)(unsigned, uint32_t, uint32_t,
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@ -2847,8 +2845,6 @@ static void gen_xpnd04_2(DisasContext *ctx)
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}
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GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
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xpnd04_1, PPC_NONE, PPC2_ISA300)
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GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
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xpnd04_2, PPC_NONE, PPC2_ISA300)
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@ -3110,6 +3106,63 @@ TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
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TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
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TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
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static void gen_VADDCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
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{
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tcg_gen_not_vec(vece, a, a);
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tcg_gen_cmp_vec(TCG_COND_LTU, vece, t, a, b);
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tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(t, vece, 1));
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}
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static void gen_VADDCUW_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
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{
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tcg_gen_not_i32(a, a);
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tcg_gen_setcond_i32(TCG_COND_LTU, t, a, b);
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}
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static void gen_VSUBCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
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{
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tcg_gen_cmp_vec(TCG_COND_GEU, vece, t, a, b);
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tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(t, vece, 1));
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}
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static void gen_VSUBCUW_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
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{
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tcg_gen_setcond_i32(TCG_COND_GEU, t, a, b);
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}
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static bool do_vx_vaddsubcuw(DisasContext *ctx, arg_VX *a, int add)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_cmp_vec, 0
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};
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static const GVecGen3 op[] = {
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{
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.fniv = gen_VSUBCUW_vec,
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.fni4 = gen_VSUBCUW_i32,
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.opt_opc = vecop_list,
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.vece = MO_32
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},
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{
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.fniv = gen_VADDCUW_vec,
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.fni4 = gen_VADDCUW_i32,
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.opt_opc = vecop_list,
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.vece = MO_32
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},
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};
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REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
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REQUIRE_VECTOR(ctx);
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tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
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avr_full_offset(a->vrb), 16, 16, &op[add]);
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return true;
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}
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TRANS(VSUBCUW, do_vx_vaddsubcuw, 0)
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TRANS(VADDCUW, do_vx_vaddsubcuw, 1)
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static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
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void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
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{
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@ -106,12 +106,11 @@ GEN_VXFORM_300(vsrv, 2, 28),
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GEN_VXFORM_300(vslv, 2, 29),
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GEN_VXFORM(vslo, 6, 16),
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GEN_VXFORM(vsro, 6, 17),
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GEN_VXFORM(vaddcuw, 0, 6),
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GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
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GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(xpnd04_1, 0, 22),
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GEN_VXFORM_300(bcdsr, 0, 23),
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GEN_VXFORM_300(bcdsr, 0, 31),
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GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
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