Hexagon (target/hexagon) Remove next_PC from runtime state
The imported files don't properly mark all CONDEXEC instructions, so we add some logic to hex_common.py to add the attribute. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-7-tsimpson@quicinc.com>
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40085901db
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613653e500
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@ -78,7 +78,6 @@ typedef struct CPUArchState {
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target_ulong gpr[TOTAL_PER_THREAD_REGS];
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target_ulong pred[NUM_PREGS];
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target_ulong branch_taken;
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target_ulong next_PC;
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/* For comparing with LLDB on target - see adjust_stack_ptrs function */
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target_ulong last_pc_dumped;
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@ -245,6 +245,10 @@ def gen_helper_function(f, tag, tagregs, tagimms):
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if i > 0: f.write(", ")
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f.write("target_ulong PC")
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i += 1
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if hex_common.helper_needs_next_PC(tag):
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if i > 0: f.write(", ")
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f.write("target_ulong next_PC")
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i += 1
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if hex_common.need_slot(tag):
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if i > 0: f.write(", ")
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f.write("uint32_t slot")
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@ -86,6 +86,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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if hex_common.need_part1(tag): def_helper_size += 1
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if hex_common.need_slot(tag): def_helper_size += 1
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if hex_common.need_PC(tag): def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
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f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
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## The return type is void
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f.write(', void' )
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@ -95,6 +96,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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if hex_common.need_part1(tag): def_helper_size += 1
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if hex_common.need_slot(tag): def_helper_size += 1
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if hex_common.need_PC(tag): def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
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f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
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## Generate the qemu DEF_HELPER type for each result
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@ -134,6 +136,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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## part1 (if needed)
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if hex_common.need_pkt_has_multi_cof(tag): f.write(', i32')
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if hex_common.need_PC(tag): f.write(', i32')
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if hex_common.helper_needs_next_PC(tag): f.write(', i32')
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if hex_common.need_slot(tag): f.write(', i32' )
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if hex_common.need_part1(tag): f.write(' , i32' )
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f.write(')\n')
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@ -612,6 +612,12 @@
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tcg_temp_free(tmp); \
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} while (0)
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#define fGEN_TCG_J2_pause(SHORTCODE) \
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do { \
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uiV = uiV; \
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \
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} while (0)
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/* r0 = asr(r1, r2):sat */
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#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
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gen_asr_r_r_sat(RdV, RsV, RtV)
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@ -631,6 +631,8 @@ def gen_tcg_func(f, tag, regs, imms):
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f.write(" TCGv slot = tcg_constant_tl(insn->slot);\n")
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if hex_common.need_PC(tag):
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f.write(" TCGv PC = tcg_constant_tl(ctx->pkt->pc);\n")
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if hex_common.helper_needs_next_PC(tag):
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f.write(" TCGv next_PC = tcg_constant_tl(ctx->next_PC);\n")
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f.write(" gen_helper_%s(" % (tag))
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i=0
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## If there is a scalar result, it is the return type
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@ -662,6 +664,7 @@ def gen_tcg_func(f, tag, regs, imms):
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if hex_common.need_pkt_has_multi_cof(tag):
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f.write(", pkt_has_multi_cof")
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if hex_common.need_PC(tag): f.write(", PC")
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if hex_common.helper_needs_next_PC(tag): f.write(", next_PC")
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if hex_common.need_slot(tag): f.write(", slot")
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if hex_common.need_part1(tag): f.write(", part1" )
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f.write(");\n")
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@ -66,6 +66,19 @@ def add_qemu_macro_attrib(name, attrib):
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macros[name].attribs.add(attrib)
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immextre = re.compile(r'f(MUST_)?IMMEXT[(]([UuSsRr])')
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def is_cond_jump(tag):
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if tag == 'J2_rte':
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return False
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if ('A_HWLOOP0_END' in attribdict[tag] or
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'A_HWLOOP1_END' in attribdict[tag]):
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return False
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return \
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re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
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def is_cond_call(tag):
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return re.compile(r"(if.*fCALL)").search(semdict[tag]) != None
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def calculate_attribs():
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add_qemu_macro_attrib('fREAD_PC', 'A_IMPLICIT_READS_PC')
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add_qemu_macro_attrib('fTRAP', 'A_IMPLICIT_READS_PC')
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@ -96,6 +109,11 @@ def calculate_attribs():
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for regtype, regid, toss, numregs in regs:
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if regtype == "P" and is_written(regid):
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attribdict[tag].add('A_WRITES_PRED_REG')
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# Mark conditional jumps and calls
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# Not all instructions are properly marked with A_CONDEXEC
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for tag in tags:
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if is_cond_jump(tag) or is_cond_call(tag):
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attribdict[tag].add('A_CONDEXEC')
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def SEMANTICS(tag, beh, sem):
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#print tag,beh,sem
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@ -211,6 +229,9 @@ def need_ea(tag):
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def need_PC(tag):
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return 'A_IMPLICIT_READS_PC' in attribdict[tag]
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def helper_needs_next_PC(tag):
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return 'A_CALL' in attribdict[tag]
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def need_pkt_has_multi_cof(tag):
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return 'A_COF' in attribdict[tag]
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@ -400,7 +400,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
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#endif
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#define fREAD_PC() (PC)
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#define fREAD_NPC() (env->next_PC & (0xfffffffe))
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#define fREAD_NPC() (next_PC & (0xfffffffe))
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#define fREAD_P0() (READ_PREG(0))
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#define fREAD_P3() (READ_PREG(3))
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@ -119,12 +119,12 @@ static void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof,
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"ignoring the second one\n");
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} else {
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fCHECK_PCALIGN(addr);
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env->next_PC = addr;
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env->gpr[HEX_REG_PC] = addr;
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env->branch_taken = 1;
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}
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} else {
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fCHECK_PCALIGN(addr);
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env->next_PC = addr;
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env->gpr[HEX_REG_PC] = addr;
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}
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}
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@ -299,7 +299,7 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1)
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}
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}
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HEX_DEBUG_LOG("Next PC = " TARGET_FMT_lx "\n", env->next_PC);
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HEX_DEBUG_LOG("Next PC = " TARGET_FMT_lx "\n", env->gpr[HEX_REG_PC]);
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HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx
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", insn = " TARGET_FMT_lx
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", hvx = " TARGET_FMT_lx "\n",
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@ -31,7 +31,6 @@
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TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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TCGv hex_pred[NUM_PREGS];
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TCGv hex_next_PC;
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TCGv hex_this_PC;
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TCGv hex_slot_cancelled;
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TCGv hex_branch_taken;
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@ -120,7 +119,6 @@ static void gen_exec_counters(DisasContext *ctx)
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static void gen_end_tb(DisasContext *ctx)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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tcg_gen_exit_tb(NULL, 0);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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@ -128,7 +126,7 @@ static void gen_end_tb(DisasContext *ctx)
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static void gen_exception_end_tb(DisasContext *ctx, int excp)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC);
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gen_exception_raw(excp);
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ctx->base.is_jmp = DISAS_NORETURN;
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@ -204,6 +202,24 @@ static bool need_pred_written(Packet *pkt)
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return check_for_attrib(pkt, A_WRITES_PRED_REG);
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}
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static bool need_next_PC(DisasContext *ctx)
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{
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Packet *pkt = ctx->pkt;
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/* Check for conditional control flow or HW loop end */
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for (int i = 0; i < pkt->num_insns; i++) {
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uint16_t opcode = pkt->insn[i].opcode;
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if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) {
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return true;
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}
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if (GET_ATTRIB(opcode, A_HWLOOP0_END) ||
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GET_ATTRIB(opcode, A_HWLOOP1_END)) {
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return true;
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}
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}
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return false;
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}
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static void gen_start_packet(DisasContext *ctx)
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{
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Packet *pkt = ctx->pkt;
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@ -211,6 +227,7 @@ static void gen_start_packet(DisasContext *ctx)
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int i;
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/* Clear out the disassembly context */
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ctx->next_PC = next_PC;
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ctx->reg_log_idx = 0;
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bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
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ctx->preg_log_idx = 0;
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@ -243,7 +260,9 @@ static void gen_start_packet(DisasContext *ctx)
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if (pkt->pkt_has_multi_cof) {
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tcg_gen_movi_tl(hex_branch_taken, 0);
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}
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tcg_gen_movi_tl(hex_next_PC, next_PC);
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if (need_next_PC(ctx)) {
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
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}
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}
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if (need_pred_written(pkt)) {
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tcg_gen_movi_tl(hex_pred_written, 0);
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@ -936,8 +955,6 @@ void hexagon_translate_init(void)
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}
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hex_pred_written = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, pred_written), "pred_written");
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hex_next_PC = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, next_PC), "next_PC");
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hex_this_PC = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, this_PC), "this_PC");
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hex_slot_cancelled = tcg_global_mem_new(cpu_env,
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@ -30,6 +30,7 @@ typedef struct DisasContext {
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DisasContextBase base;
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Packet *pkt;
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Insn *insn;
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uint32_t next_PC;
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uint32_t mem_idx;
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uint32_t num_packets;
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uint32_t num_insns;
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@ -134,7 +135,6 @@ static inline void ctx_log_qreg_write(DisasContext *ctx,
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extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_pred[NUM_PREGS];
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extern TCGv hex_next_PC;
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extern TCGv hex_this_PC;
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extern TCGv hex_slot_cancelled;
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extern TCGv hex_branch_taken;
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