Queued target/sh4 patches
-----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEd0YmQqnvlP0Pdxltupx4Bh3djJsFAlktxAoVHGF1cmVsaWVu QGF1cmVsMzIubmV0AAoJELqceAYd3Yyb5mAQAJgSmSIzZIva8RAmP/SznKvwpyUn Da/osDSNbd+R6PRjqZ8TnIv0wKl8n6iE/Vz+LqviS7CRz/WAoiEm6HmtyWITyEZ7 3pRCfYTFU6uoyOXmc/d/VQm15kvMIf+VVWhpZ8XV2un7lKQyqBEx3GNEPkGqpiqJ 5G5122xgiA/ck50ApGqzOt5/u1DGedac+4WKaSIAkoPrVCuv6+8qR28X9b9UZHMJ K+NLgPmScO03RKdNTFkHqW7hZMR/nlcZfIxc4Ez7XAzkUtIjtgYi1apUDaogKd87 plCmDqCXr3KxLYNj+kRl8xsoVyU099+tCCt5QO7ppR4fvp04MMZLR+PMkPtPvrsv X1/eVv5gKEDj33AKiA4UNE+pwvKZxnv+jHv1RhDPq7W6xNgNkN2fgxBIzGDvEJZZ 9azno8JQBP98AyL5z9f+91ARQ6nODZbUrwXzO2hqWm+lffXTBSxK1txJ/iqg0lF4 yURnfy+tVBIlgyotZycfxpe2W/NjwwKUjwaEF3KIach85fSp4dqETpLHyEQUGeaY cFbYukSYiTkiUowJVFpA1ycD5JNQai1X8aeimj0NxhwGuIvh6yrEjYcHWsmSsho1 p+uoxdXaXOBxyW8zT6FQM/H1pVh/0R9rVcsrlsZJcdR8T1qrDeXamwOQPjYkoAij G9FkHhF220YBjhfM =dVHt -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/aurel/tags/pull-target-sh4-20170530' into staging Queued target/sh4 patches # gpg: Signature made Tue 30 May 2017 20:12:10 BST # gpg: using RSA key 0xBA9C78061DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-target-sh4-20170530: target/sh4: fix RTE instruction delay slot target/sh4: ignore interrupts in a delay slot target/sh4: introduce DELAY_SLOT_MASK target/sh4: fix reset when using a kernel and an initrd target/sh4: log unauthorized accesses using qemu_log_mask Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
61462af65a
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@ -91,8 +91,10 @@
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#define FPSCR_RM_NEAREST (0 << 0)
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#define FPSCR_RM_ZERO (1 << 0)
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#define DELAY_SLOT_MASK 0x7
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#define DELAY_SLOT (1 << 0)
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#define DELAY_SLOT_CONDITIONAL (1 << 1)
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#define DELAY_SLOT_RTE (1 << 2)
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typedef struct tlb_t {
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uint32_t vpn; /* virtual page number */
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@ -263,7 +265,13 @@ void cpu_load_tlb(CPUSH4State * env);
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
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{
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return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
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/* The instruction in a RTE delay slot is fetched in privileged
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mode, but executed in user mode. */
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if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
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return 0;
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} else {
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return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
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}
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}
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#include "exec/cpu-all.h"
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@ -380,7 +388,7 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) /* Bits 0-1 */
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*flags = (env->flags & DELAY_SLOT_MASK) /* Bits 0- 2 */
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| (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
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| (env->sr & (1u << SR_FD)) /* Bit 15 */
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@ -21,6 +21,7 @@
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/log.h"
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#include "sysemu/sysemu.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/sh4/sh_intc.h"
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@ -92,7 +93,14 @@ void superh_cpu_do_interrupt(CPUState *cs)
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if (env->sr & (1u << SR_BL)) {
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if (do_exp && cs->exception_index != 0x1e0) {
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cs->exception_index = 0x000; /* masked exception -> reset */
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/* In theory a masked exception generates a reset exception,
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which in turn jumps to the reset vector. However this only
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works when using a bootloader. When using a kernel and an
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initrd, they need to be reloaded and the program counter
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should be loaded with the kernel entry point.
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qemu_system_reset_request takes care of that. */
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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}
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if (do_irq && !env->in_sleep) {
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return; /* masked */
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@ -164,11 +172,11 @@ void superh_cpu_do_interrupt(CPUState *cs)
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env->sgr = env->gregs[15];
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env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
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if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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if (env->flags & DELAY_SLOT_MASK) {
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/* Branch instruction should be executed again before delay slot. */
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env->spc -= 2;
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/* Clear flags for exception/interrupt routine. */
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env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
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env->flags &= ~DELAY_SLOT_MASK;
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}
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if (do_exp) {
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@ -420,7 +428,7 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
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if (!(env->sr & (1u << SR_MD))
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&& (address < 0xe0000000 || address >= 0xe4000000)) {
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/* Unauthorized access in user mode (only store queues are available) */
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fprintf(stderr, "Unauthorized access\n");
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qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
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if (rw == 0)
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return MMU_DADDR_ERROR_READ;
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else if (rw == 1)
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@ -863,8 +871,16 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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superh_cpu_do_interrupt(cs);
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return true;
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SuperHCPU *cpu = SUPERH_CPU(cs);
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CPUSH4State *env = &cpu->env;
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/* Delay slots are indivisible, ignore interrupts */
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if (env->flags & DELAY_SLOT_MASK) {
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return false;
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} else {
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superh_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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@ -185,6 +185,9 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f,
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} else if (env->flags & DELAY_SLOT_CONDITIONAL) {
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cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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env->delayed_pc);
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} else if (env->flags & DELAY_SLOT_RTE) {
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cpu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n",
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env->delayed_pc);
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}
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}
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@ -217,8 +220,7 @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
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if (ctx->delayed_pc != (uint32_t) -1) {
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tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
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}
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if ((ctx->tbflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
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!= ctx->envflags) {
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if ((ctx->tbflags & DELAY_SLOT_MASK) != ctx->envflags) {
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tcg_gen_movi_i32(cpu_flags, ctx->envflags);
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}
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}
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@ -329,7 +331,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
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#define CHECK_NOT_DELAY_SLOT \
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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if (ctx->envflags & DELAY_SLOT_MASK) { \
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gen_save_cpu_state(ctx, true); \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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ctx->bstate = BS_EXCP; \
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@ -339,7 +341,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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#define CHECK_PRIVILEGED \
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if (IS_USER(ctx)) { \
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gen_save_cpu_state(ctx, true); \
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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if (ctx->envflags & DELAY_SLOT_MASK) { \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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} else { \
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gen_helper_raise_illegal_instruction(cpu_env); \
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@ -351,7 +353,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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#define CHECK_FPU_ENABLED \
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if (ctx->tbflags & (1u << SR_FD)) { \
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gen_save_cpu_state(ctx, true); \
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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if (ctx->envflags & DELAY_SLOT_MASK) { \
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gen_helper_raise_slot_fpu_disable(cpu_env); \
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} else { \
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gen_helper_raise_fpu_disable(cpu_env); \
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@ -428,8 +430,9 @@ static void _decode_opc(DisasContext * ctx)
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CHECK_NOT_DELAY_SLOT
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gen_write_sr(cpu_ssr);
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tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
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ctx->envflags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT_RTE;
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ctx->delayed_pc = (uint32_t) - 1;
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ctx->bstate = BS_STOP;
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return;
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case 0x0058: /* sets */
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tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));
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@ -1784,7 +1787,7 @@ static void _decode_opc(DisasContext * ctx)
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fflush(stderr);
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#endif
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gen_save_cpu_state(ctx, true);
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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if (ctx->envflags & DELAY_SLOT_MASK) {
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gen_helper_raise_slot_illegal_instruction(cpu_env);
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} else {
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gen_helper_raise_illegal_instruction(cpu_env);
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@ -1798,14 +1801,14 @@ static void decode_opc(DisasContext * ctx)
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_decode_opc(ctx);
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if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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if (old_flags & DELAY_SLOT_MASK) {
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/* go out of the delay slot */
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ctx->envflags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
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ctx->envflags &= ~DELAY_SLOT_MASK;
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tcg_gen_movi_i32(cpu_flags, ctx->envflags);
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ctx->bstate = BS_BRANCH;
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if (old_flags & DELAY_SLOT_CONDITIONAL) {
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gen_delayed_conditional_jump(ctx);
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} else if (old_flags & DELAY_SLOT) {
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} else {
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gen_jump(ctx);
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}
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@ -1824,7 +1827,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
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pc_start = tb->pc;
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ctx.pc = pc_start;
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ctx.tbflags = (uint32_t)tb->flags;
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ctx.envflags = tb->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
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ctx.envflags = tb->flags & DELAY_SLOT_MASK;
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ctx.bstate = BS_NONE;
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ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
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/* We don't know if the delayed pc came from a dynamic or static branch,
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