From 61aa9a697a1ec9b102e86cb7ea96876e6f20afe3 Mon Sep 17 00:00:00 2001 From: Nikunj A Dadhania Date: Mon, 27 Feb 2017 10:27:59 +0530 Subject: [PATCH] target/ppc: add ov32 flag for multiply low insns For Multiply Word: SO, OV, and OV32 bits reflects overflow of the 32-bit result For Multiply DoubleWord: SO, OV, and OV32 bits reflects overflow of the 64-bit result Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d4d9941f08..ccf3bff817 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1285,6 +1285,9 @@ static void gen_mullwo(DisasContext *ctx) tcg_gen_sari_i32(t0, t0, 31); tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); tcg_gen_extu_i32_tl(cpu_ov, t0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ov32, cpu_ov); + } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); tcg_temp_free_i32(t0); @@ -1346,6 +1349,9 @@ static void gen_mulldo(DisasContext *ctx) tcg_gen_sari_i64(t0, t0, 63); tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ov32, cpu_ov); + } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); tcg_temp_free_i64(t0);