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mips hw/: Don't use CPUState 

Scripted conversion:
  for file in hw/mips_*.[hc]; do
    sed -i "s/CPUState/CPUMIPSState/g" $file
  done

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:23 +01:00
parent ee11850732
commit 61c56c8c86
8 changed files with 34 additions and 34 deletions
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4
hw/mips_cpudevs.h
View File

@ -7,9 +7,9 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
/* mips_int.c */ /* mips_int.c */
void cpu_mips_irq_init_cpu(CPUState *env); void cpu_mips_irq_init_cpu(CPUMIPSState *env);
/* mips_timer.c */ /* mips_timer.c */
void cpu_mips_clock_init(CPUState *); void cpu_mips_clock_init(CPUMIPSState *);
#endif #endif

10
hw/mips_fulong2e.c
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@ -102,7 +102,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_end(ap); va_end(ap);
} }
static int64_t load_kernel (CPUState *env) static int64_t load_kernel (CPUMIPSState *env)
{ {
int64_t kernel_entry, kernel_low, kernel_high; int64_t kernel_entry, kernel_low, kernel_high;
int index = 0; int index = 0;
@ -168,7 +168,7 @@ static int64_t load_kernel (CPUState *env)
return kernel_entry; return kernel_entry;
} }
static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr) static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
{ {
uint32_t *p; uint32_t *p;
@ -198,7 +198,7 @@ static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUMIPSState *env = opaque;
cpu_state_reset(env); cpu_state_reset(env);
/* TODO: 2E reset stuff */ /* TODO: 2E reset stuff */
@ -248,7 +248,7 @@ static void network_init (void)
static void cpu_request_exit(void *opaque, int irq, int level) static void cpu_request_exit(void *opaque, int irq, int level)
{ {
CPUState *env = cpu_single_env; CPUMIPSState *env = cpu_single_env;
if (env && level) { if (env && level) {
cpu_exit(env); cpu_exit(env);
@ -272,7 +272,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
i2c_bus *smbus; i2c_bus *smbus;
int i; int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
CPUState *env; CPUMIPSState *env;
/* init CPUs */ /* init CPUs */
if (cpu_model == NULL) { if (cpu_model == NULL) {

6
hw/mips_int.c
View File

@ -26,7 +26,7 @@
static void cpu_mips_irq_request(void *opaque, int irq, int level) static void cpu_mips_irq_request(void *opaque, int irq, int level)
{ {
CPUState *env = (CPUState *)opaque; CPUMIPSState *env = (CPUMIPSState *)opaque;
if (irq < 0 || irq > 7) if (irq < 0 || irq > 7)
return; return;
@ -44,7 +44,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
} }
} }
void cpu_mips_irq_init_cpu(CPUState *env) void cpu_mips_irq_init_cpu(CPUMIPSState *env)
{ {
qemu_irq *qi; qemu_irq *qi;
int i; int i;
@ -55,7 +55,7 @@ void cpu_mips_irq_init_cpu(CPUState *env)
} }
} }
void cpu_mips_soft_irq(CPUState *env, int irq, int level) void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
{ {
if (irq < 0 || irq > 2) { if (irq < 0 || irq > 2) {
return; return;

6
hw/mips_jazz.c
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@ -50,7 +50,7 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUMIPSState *env = opaque;
cpu_state_reset(env); cpu_state_reset(env);
} }
@ -97,7 +97,7 @@ static const MemoryRegionOps dma_dummy_ops = {
static void cpu_request_exit(void *opaque, int irq, int level) static void cpu_request_exit(void *opaque, int irq, int level)
{ {
CPUState *env = cpu_single_env; CPUMIPSState *env = cpu_single_env;
if (env && level) { if (env && level) {
cpu_exit(env); cpu_exit(env);
@ -112,7 +112,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
{ {
char *filename; char *filename;
int bios_size, n; int bios_size, n;
CPUState *env; CPUMIPSState *env;
qemu_irq *rc4030, *i8259; qemu_irq *rc4030, *i8259;
rc4030_dma *dmas; rc4030_dma *dmas;
void* rc4030_opaque; void* rc4030_opaque;

10
hw/mips_malta.c
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@ -500,7 +500,7 @@ static void network_init(void)
a3 - RAM size in bytes a3 - RAM size in bytes
*/ */
static void write_bootloader (CPUState *env, uint8_t *base, static void write_bootloader (CPUMIPSState *env, uint8_t *base,
int64_t kernel_entry) int64_t kernel_entry)
{ {
uint32_t *p; uint32_t *p;
@ -736,7 +736,7 @@ static int64_t load_kernel (void)
return kernel_entry; return kernel_entry;
} }
static void malta_mips_config(CPUState *env) static void malta_mips_config(CPUMIPSState *env)
{ {
env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC); ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
@ -744,7 +744,7 @@ static void malta_mips_config(CPUState *env)
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUMIPSState *env = opaque;
cpu_state_reset(env); cpu_state_reset(env);
/* The bootloader does not need to be rewritten as it is located in a /* The bootloader does not need to be rewritten as it is located in a
@ -759,7 +759,7 @@ static void main_cpu_reset(void *opaque)
static void cpu_request_exit(void *opaque, int irq, int level) static void cpu_request_exit(void *opaque, int irq, int level)
{ {
CPUState *env = cpu_single_env; CPUMIPSState *env = cpu_single_env;
if (env && level) { if (env && level) {
cpu_exit(env); cpu_exit(env);
@ -781,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size,
int64_t kernel_entry; int64_t kernel_entry;
PCIBus *pci_bus; PCIBus *pci_bus;
ISABus *isa_bus; ISABus *isa_bus;
CPUState *env; CPUMIPSState *env;
qemu_irq *isa_irq; qemu_irq *isa_irq;
qemu_irq *cpu_exit_irq; qemu_irq *cpu_exit_irq;
int piix4_devfn; int piix4_devfn;

6
hw/mips_mipssim.c
View File

@ -46,7 +46,7 @@ static struct _loaderparams {
} loaderparams; } loaderparams;
typedef struct ResetData { typedef struct ResetData {
CPUState *env; CPUMIPSState *env;
uint64_t vector; uint64_t vector;
} ResetData; } ResetData;
@ -105,7 +105,7 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUMIPSState *env = s->env;
cpu_state_reset(env); cpu_state_reset(env);
env->active_tc.PC = s->vector & ~(target_ulong)1; env->active_tc.PC = s->vector & ~(target_ulong)1;
@ -140,7 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1);
CPUState *env; CPUMIPSState *env;
ResetData *reset_info; ResetData *reset_info;
int bios_size; int bios_size;

6
hw/mips_r4k.c
View File

@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = {
}; };
typedef struct ResetData { typedef struct ResetData {
CPUState *env; CPUMIPSState *env;
uint64_t vector; uint64_t vector;
} ResetData; } ResetData;
@ -143,7 +143,7 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUMIPSState *env = s->env;
cpu_state_reset(env); cpu_state_reset(env);
env->active_tc.PC = s->vector; env->active_tc.PC = s->vector;
@ -162,7 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size,
MemoryRegion *bios; MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1); MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size; int bios_size;
CPUState *env; CPUMIPSState *env;
ResetData *reset_info; ResetData *reset_info;
int i; int i;
qemu_irq *i8259; qemu_irq *i8259;

20
hw/mips_timer.c
View File

@ -27,7 +27,7 @@
#define TIMER_FREQ 100 * 1000 * 1000 #define TIMER_FREQ 100 * 1000 * 1000
/* XXX: do not use a global */ /* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUState *env) uint32_t cpu_mips_get_random (CPUMIPSState *env)
{ {
static uint32_t lfsr = 1; static uint32_t lfsr = 1;
static uint32_t prev_idx = 0; static uint32_t prev_idx = 0;
@ -42,7 +42,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
} }
/* MIPS R4K timer */ /* MIPS R4K timer */
static void cpu_mips_timer_update(CPUState *env) static void cpu_mips_timer_update(CPUMIPSState *env)
{ {
uint64_t now, next; uint64_t now, next;
uint32_t wait; uint32_t wait;
@ -55,7 +55,7 @@ static void cpu_mips_timer_update(CPUState *env)
} }
/* Expire the timer. */ /* Expire the timer. */
static void cpu_mips_timer_expire(CPUState *env) static void cpu_mips_timer_expire(CPUMIPSState *env)
{ {
cpu_mips_timer_update(env); cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2) { if (env->insn_flags & ISA_MIPS32R2) {
@ -64,7 +64,7 @@ static void cpu_mips_timer_expire(CPUState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
} }
uint32_t cpu_mips_get_count (CPUState *env) uint32_t cpu_mips_get_count (CPUMIPSState *env)
{ {
if (env->CP0_Cause & (1 << CP0Ca_DC)) { if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count; return env->CP0_Count;
@ -83,7 +83,7 @@ uint32_t cpu_mips_get_count (CPUState *env)
} }
} }
void cpu_mips_store_count (CPUState *env, uint32_t count) void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
{ {
if (env->CP0_Cause & (1 << CP0Ca_DC)) if (env->CP0_Cause & (1 << CP0Ca_DC))
env->CP0_Count = count; env->CP0_Count = count;
@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count)
} }
} }
void cpu_mips_store_compare (CPUState *env, uint32_t value) void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
{ {
env->CP0_Compare = value; env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
@ -107,12 +107,12 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value)
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
} }
void cpu_mips_start_count(CPUState *env) void cpu_mips_start_count(CPUMIPSState *env)
{ {
cpu_mips_store_count(env, env->CP0_Count); cpu_mips_store_count(env, env->CP0_Count);
} }
void cpu_mips_stop_count(CPUState *env) void cpu_mips_stop_count(CPUMIPSState *env)
{ {
/* Store the current value */ /* Store the current value */
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock), env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
@ -121,7 +121,7 @@ void cpu_mips_stop_count(CPUState *env)
static void mips_timer_cb (void *opaque) static void mips_timer_cb (void *opaque)
{ {
CPUState *env; CPUMIPSState *env;
env = opaque; env = opaque;
#if 0 #if 0
@ -139,7 +139,7 @@ static void mips_timer_cb (void *opaque)
env->CP0_Count--; env->CP0_Count--;
} }
void cpu_mips_clock_init (CPUState *env) void cpu_mips_clock_init (CPUMIPSState *env)
{ {
env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env); env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
env->CP0_Compare = 0; env->CP0_Compare = 0;