From 84c9d9d1e932460c1d8c60b1d96a58d1e47ec4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 13 Apr 2012 18:30:29 +0200 Subject: [PATCH 01/12] MAINTAINERS: Downgrade target-m68k to Odd Fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit m68k patches are not being handled, so let's downgrade to Odd Fixes. Signed-off-by: Andreas Färber Acked-by: Paul Brook --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cce37e797f..8ae915847a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -78,7 +78,7 @@ F: target-lm32/ M68K M: Paul Brook -S: Maintained +S: Odd Fixes F: target-m68k/ MicroBlaze From 2c9b7d1ab4e06ab742f669366c70d97e54598c36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 13 Apr 2012 18:33:43 +0200 Subject: [PATCH 02/12] MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Patches are not being handled, so let's downgrade to Odd Fixes. Signed-off-by: Andreas Färber Acked-by: Aurélien Jarno --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8ae915847a..32d8dc761a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -88,7 +88,7 @@ F: target-microblaze/ MIPS M: Aurelien Jarno -S: Maintained +S: Odd Fixes F: target-mips/ PowerPC @@ -104,7 +104,7 @@ F: target-s390x/ SH4 M: Aurelien Jarno -S: Maintained +S: Odd Fixes F: target-sh4/ SPARC From 339894bec9bb99aaeb695173006322c37a102408 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 11 Feb 2012 17:26:17 +0100 Subject: [PATCH 03/12] target-sh4: QOM'ify CPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Embed CPUSH4State as first member of SuperHCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber Reviewed-by: Peter Maydell --- Makefile.target | 1 + target-sh4/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++ target-sh4/cpu.c | 60 ++++++++++++++++++++++++++++++++++++ target-sh4/cpu.h | 2 ++ target-sh4/translate.c | 4 ++- 5 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 target-sh4/cpu-qom.h create mode 100644 target-sh4/cpu.c diff --git a/Makefile.target b/Makefile.target index 4fbbabfe24..ace1182ca1 100644 --- a/Makefile.target +++ b/Makefile.target @@ -98,6 +98,7 @@ libobj-$(TARGET_CRIS) += cpu.o libobj-$(TARGET_LM32) += cpu.o libobj-$(TARGET_MICROBLAZE) += cpu.o libobj-$(TARGET_S390X) += cpu.o +libobj-$(TARGET_SH4) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o libobj-y += cpu.o diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h new file mode 100644 index 0000000000..c41164aa22 --- /dev/null +++ b/target-sh4/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU SuperH CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ +#ifndef QEMU_SUPERH_CPU_QOM_H +#define QEMU_SUPERH_CPU_QOM_H + +#include "qemu/cpu.h" + +#define TYPE_SUPERH_CPU "superh-cpu" + +#define SUPERH_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU) +#define SUPERH_CPU(obj) \ + OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU) +#define SUPERH_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU) + +/** + * SuperHCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A SuperH CPU model. + */ +typedef struct SuperHCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); +} SuperHCPUClass; + +/** + * SuperHCPU: + * @env: #CPUSH4State + * + * A SuperH CPU. + */ +typedef struct SuperHCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUSH4State env; +} SuperHCPU; + +static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) +{ + return SUPERH_CPU(container_of(env, SuperHCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) + + +#endif diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c new file mode 100644 index 0000000000..e110f982cf --- /dev/null +++ b/target-sh4/cpu.c @@ -0,0 +1,60 @@ +/* + * QEMU SuperH CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "cpu.h" +#include "qemu-common.h" + + +/* CPUClass::reset() */ +static void superh_cpu_reset(CPUState *s) +{ + SuperHCPU *cpu = SUPERH_CPU(s); + SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); + CPUSH4State *env = &cpu->env; + + scc->parent_reset(s); + + cpu_state_reset(env); +} + +static void superh_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); + + scc->parent_reset = cc->reset; + cc->reset = superh_cpu_reset; +} + +static const TypeInfo superh_cpu_type_info = { + .name = TYPE_SUPERH_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(SuperHCPU), + .abstract = false, + .class_size = sizeof(SuperHCPUClass), + .class_init = superh_cpu_class_init, +}; + +static void superh_cpu_register_types(void) +{ + type_register_static(&superh_cpu_type_info); +} + +type_init(superh_cpu_register_types) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 965536dce5..b6768f1648 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -189,6 +189,8 @@ typedef struct CPUSH4State { memory_content **movcal_backup_tail; } CPUSH4State; +#include "cpu-qom.h" + CPUSH4State *cpu_sh4_init(const char *cpu_model); int cpu_sh4_exec(CPUSH4State * s); int cpu_sh4_signal_handler(int host_signum, void *pinfo, diff --git a/target-sh4/translate.c b/target-sh4/translate.c index a337beb9ef..6309e85b69 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -267,13 +267,15 @@ static void cpu_register(CPUSH4State *env, const sh4_def_t *def) CPUSH4State *cpu_sh4_init(const char *cpu_model) { + SuperHCPU *cpu; CPUSH4State *env; const sh4_def_t *def; def = cpu_sh4_find_by_name(cpu_model); if (!def) return NULL; - env = g_malloc0(sizeof(CPUSH4State)); + cpu = SUPERH_CPU(object_new(TYPE_SUPERH_CPU)); + env = &cpu->env; env->features = def->features; cpu_exec_init(env); env->movcal_backup_tail = &(env->movcal_backup); From c4bb0f99e797e5e5720c27544a2fc61a0b722023 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 13 Apr 2012 02:16:02 +0200 Subject: [PATCH 04/12] target-sh4: QOM'ify CPU reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code from cpu_state_reset() to QOM superh_cpu_reset(). Signed-off-by: Andreas Färber Reviewed-by: Peter Maydell --- target-sh4/cpu.c | 21 ++++++++++++++++++++- target-sh4/translate.c | 22 ++-------------------- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index e110f982cf..84d46728aa 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -1,6 +1,7 @@ /* * QEMU SuperH CPU * + * Copyright (c) 2005 Samuel Tardieu * Copyright (c) 2012 SUSE LINUX Products GmbH * * This library is free software; you can redistribute it and/or @@ -29,9 +30,27 @@ static void superh_cpu_reset(CPUState *s) SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); CPUSH4State *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + scc->parent_reset(s); - cpu_state_reset(env); + memset(env, 0, offsetof(CPUSH4State, breakpoints)); + tlb_flush(env, 1); + + env->pc = 0xA0000000; +#if defined(CONFIG_USER_ONLY) + env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ +#else + env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; + env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + set_flush_to_zero(1, &env->fp_status); +#endif + set_default_nan_mode(1, &env->fp_status); } static void superh_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 6309e85b69..d0568e2964 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -180,25 +180,7 @@ void cpu_dump_state(CPUSH4State * env, FILE * f, void cpu_state_reset(CPUSH4State *env) { - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - memset(env, 0, offsetof(CPUSH4State, breakpoints)); - tlb_flush(env, 1); - - env->pc = 0xA0000000; -#if defined(CONFIG_USER_ONLY) - env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ -#else - env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; - env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - set_flush_to_zero(1, &env->fp_status); -#endif - set_default_nan_mode(1, &env->fp_status); + cpu_reset(ENV_GET_CPU(env)); } typedef struct { @@ -281,7 +263,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) env->movcal_backup_tail = &(env->movcal_backup); sh4_translate_init(); env->cpu_model_str = cpu_model; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); cpu_register(env, def); qemu_init_vcpu(env); return env; From 2b4b49065670b46b424a329da5d35838180fc209 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 13 Apr 2012 02:32:12 +0200 Subject: [PATCH 05/12] target-sh4: Start QOM'ifying CPU init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code from cpu_sh4_init() into a QOM initfn. Signed-off-by: Andreas Färber --- target-sh4/cpu.c | 11 +++++++++++ target-sh4/translate.c | 2 -- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 84d46728aa..a1a177fa88 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -53,6 +53,16 @@ static void superh_cpu_reset(CPUState *s) set_default_nan_mode(1, &env->fp_status); } +static void superh_cpu_initfn(Object *obj) +{ + SuperHCPU *cpu = SUPERH_CPU(obj); + CPUSH4State *env = &cpu->env; + + cpu_exec_init(env); + + env->movcal_backup_tail = &(env->movcal_backup); +} + static void superh_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -66,6 +76,7 @@ static const TypeInfo superh_cpu_type_info = { .name = TYPE_SUPERH_CPU, .parent = TYPE_CPU, .instance_size = sizeof(SuperHCPU), + .instance_init = superh_cpu_initfn, .abstract = false, .class_size = sizeof(SuperHCPUClass), .class_init = superh_cpu_class_init, diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d0568e2964..d25f0c5a29 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -259,8 +259,6 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) cpu = SUPERH_CPU(object_new(TYPE_SUPERH_CPU)); env = &cpu->env; env->features = def->features; - cpu_exec_init(env); - env->movcal_backup_tail = &(env->movcal_backup); sh4_translate_init(); env->cpu_model_str = cpu_model; cpu_reset(CPU(cpu)); From b9e7a234343501e2498680fd7bc0cd2aad947560 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 15 Apr 2012 00:35:50 +0200 Subject: [PATCH 06/12] target-m68k: QOM'ify CPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Embed CPUM68KState as first member of QOM M68kCPU. Drop cpu_m68k_close() in favor of object_delete(). Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier --- Makefile.target | 1 + target-m68k/cpu-qom.h | 70 +++++++++++++++++++++++++++++++++++++++++++ target-m68k/cpu.c | 60 +++++++++++++++++++++++++++++++++++++ target-m68k/cpu.h | 3 +- target-m68k/helper.c | 11 +++---- 5 files changed, 137 insertions(+), 8 deletions(-) create mode 100644 target-m68k/cpu-qom.h create mode 100644 target-m68k/cpu.c diff --git a/Makefile.target b/Makefile.target index ace1182ca1..e735064be7 100644 --- a/Makefile.target +++ b/Makefile.target @@ -96,6 +96,7 @@ libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o libobj-$(TARGET_ARM) += cpu.o libobj-$(TARGET_CRIS) += cpu.o libobj-$(TARGET_LM32) += cpu.o +libobj-$(TARGET_M68K) += cpu.o libobj-$(TARGET_MICROBLAZE) += cpu.o libobj-$(TARGET_S390X) += cpu.o libobj-$(TARGET_SH4) += cpu.o diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h new file mode 100644 index 0000000000..805786b04d --- /dev/null +++ b/target-m68k/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU Motorola 68k CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ +#ifndef QEMU_M68K_CPU_QOM_H +#define QEMU_M68K_CPU_QOM_H + +#include "qemu/cpu.h" + +#define TYPE_M68K_CPU "m68k-cpu" + +#define M68K_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(M68kCPUClass, (klass), TYPE_M68K_CPU) +#define M68K_CPU(obj) \ + OBJECT_CHECK(M68kCPU, (obj), TYPE_M68K_CPU) +#define M68K_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(M68kCPUClass, (obj), TYPE_M68K_CPU) + +/** + * M68kCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A Motorola 68k CPU model. + */ +typedef struct M68kCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); +} M68kCPUClass; + +/** + * M68kCPU: + * @env: #CPUM68KState + * + * A Motorola 68k CPU. + */ +typedef struct M68kCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUM68KState env; +} M68kCPU; + +static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) +{ + return M68K_CPU(container_of(env, M68kCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) + + +#endif diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c new file mode 100644 index 0000000000..457c5c1940 --- /dev/null +++ b/target-m68k/cpu.c @@ -0,0 +1,60 @@ +/* + * QEMU Motorola 68k CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "cpu.h" +#include "qemu-common.h" + + +/* CPUClass::reset() */ +static void m68k_cpu_reset(CPUState *s) +{ + M68kCPU *cpu = M68K_CPU(s); + M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); + CPUM68KState *env = &cpu->env; + + mcc->parent_reset(s); + + cpu_state_reset(env); +} + +static void m68k_cpu_class_init(ObjectClass *c, void *data) +{ + M68kCPUClass *mcc = M68K_CPU_CLASS(c); + CPUClass *cc = CPU_CLASS(c); + + mcc->parent_reset = cc->reset; + cc->reset = m68k_cpu_reset; +} + +static const TypeInfo m68k_cpu_type_info = { + .name = TYPE_M68K_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(M68kCPU), + .abstract = false, + .class_size = sizeof(M68kCPUClass), + .class_init = m68k_cpu_class_init, +}; + +static void m68k_cpu_register_types(void) +{ + type_register_static(&m68k_cpu_type_info); +} + +type_init(m68k_cpu_register_types) diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 6696e308f8..5e6ee50969 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -116,10 +116,11 @@ typedef struct CPUM68KState { uint32_t features; } CPUM68KState; +#include "cpu-qom.h" + void m68k_tcg_init(void); CPUM68KState *cpu_m68k_init(const char *cpu_model); int cpu_m68k_exec(CPUM68KState *s); -void cpu_m68k_close(CPUM68KState *s); void do_interrupt(CPUM68KState *env1); void do_interrupt_m68k_hardirq(CPUM68KState *env1); /* you can call this signal handler from your SIGBUS and SIGSEGV diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 1feed9be67..e91acdbf0d 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -164,10 +164,12 @@ void cpu_state_reset(CPUM68KState *env) CPUM68KState *cpu_m68k_init(const char *cpu_model) { + M68kCPU *cpu; CPUM68KState *env; static int inited; - env = g_malloc0(sizeof(CPUM68KState)); + cpu = M68K_CPU(object_new(TYPE_M68K_CPU)); + env = &cpu->env; cpu_exec_init(env); if (!inited) { inited = 1; @@ -177,7 +179,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) env->cpu_model_str = cpu_model; if (cpu_m68k_set_model(env, cpu_model) < 0) { - cpu_m68k_close(env); + object_delete(OBJECT(cpu)); return NULL; } @@ -186,11 +188,6 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) return env; } -void cpu_m68k_close(CPUM68KState *env) -{ - g_free(env); -} - void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) { int flags; From 11c1986817fa8ec515b87291445786734f78e4e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 15 Apr 2012 00:59:50 +0200 Subject: [PATCH 07/12] target-m68k: QOM'ify CPU reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code from cpu_state_reset() into QOM m68k_cpu_reset(). Signed-off-by: Andreas Färber Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier --- target-m68k/cpu.c | 16 +++++++++++++++- target-m68k/helper.c | 18 ++---------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 457c5c1940..e599ece430 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -29,9 +29,23 @@ static void m68k_cpu_reset(CPUState *s) M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); CPUM68KState *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + mcc->parent_reset(s); - cpu_state_reset(env); + memset(env, 0, offsetof(CPUM68KState, breakpoints)); +#if !defined(CONFIG_USER_ONLY) + env->sr = 0x2700; +#endif + m68k_switch_sp(env); + /* ??? FP regs should be initialized to NaN. */ + env->cc_op = CC_OP_FLAGS; + /* TODO: We should set PC from the interrupt vector. */ + env->pc = 0; + tlb_flush(env, 1); } static void m68k_cpu_class_init(ObjectClass *c, void *data) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index e91acdbf0d..69fb147526 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -145,21 +145,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name) void cpu_state_reset(CPUM68KState *env) { - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - memset(env, 0, offsetof(CPUM68KState, breakpoints)); -#if !defined (CONFIG_USER_ONLY) - env->sr = 0x2700; -#endif - m68k_switch_sp(env); - /* ??? FP regs should be initialized to NaN. */ - env->cc_op = CC_OP_FLAGS; - /* TODO: We should set PC from the interrupt vector. */ - env->pc = 0; - tlb_flush(env, 1); + cpu_reset(ENV_GET_CPU(env)); } CPUM68KState *cpu_m68k_init(const char *cpu_model) @@ -183,7 +169,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) return NULL; } - cpu_state_reset(env); + cpu_reset(ENV_GET_CPU(env)); qemu_init_vcpu(env); return env; } From 9b7060396e16b0b5a81e21373f27e63bdcacb5bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 15 Apr 2012 01:10:56 +0200 Subject: [PATCH 08/12] target-m68k: Start QOM'ifying CPU init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move model-independent code from cpu_m68k_init() into a QOM initfn. Signed-off-by: Andreas Färber Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier --- target-m68k/cpu.c | 9 +++++++++ target-m68k/helper.c | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index e599ece430..0bb1b2c630 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -48,6 +48,14 @@ static void m68k_cpu_reset(CPUState *s) tlb_flush(env, 1); } +static void m68k_cpu_initfn(Object *obj) +{ + M68kCPU *cpu = M68K_CPU(obj); + CPUM68KState *env = &cpu->env; + + cpu_exec_init(env); +} + static void m68k_cpu_class_init(ObjectClass *c, void *data) { M68kCPUClass *mcc = M68K_CPU_CLASS(c); @@ -61,6 +69,7 @@ static const TypeInfo m68k_cpu_type_info = { .name = TYPE_M68K_CPU, .parent = TYPE_CPU, .instance_size = sizeof(M68kCPU), + .instance_init = m68k_cpu_initfn, .abstract = false, .class_size = sizeof(M68kCPUClass), .class_init = m68k_cpu_class_init, diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 69fb147526..e850d53d40 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -156,7 +156,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) cpu = M68K_CPU(object_new(TYPE_M68K_CPU)); env = &cpu->env; - cpu_exec_init(env); + if (!inited) { inited = 1; m68k_tcg_init(); From 11150915fcfc44aaf35c807eaa16599eabc9e718 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 15 Apr 2012 03:30:10 +0200 Subject: [PATCH 09/12] target-m68k: Add QOM CPU subclasses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code from cpu_m68k_set_model() into model-specific initfns and inline the remaining parts into cpu_m68k_init(). Let m68k_cpu_list() print CPU classes alphabetically except for "any". Signed-off-by: Andreas Färber Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier --- target-m68k/cpu.c | 89 ++++++++++++++++++++++++++++- target-m68k/helper.c | 132 +++++++++++++++---------------------------- 2 files changed, 134 insertions(+), 87 deletions(-) diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 0bb1b2c630..3e70bb0ead 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -22,6 +22,11 @@ #include "qemu-common.h" +static void m68k_set_feature(CPUM68KState *env, int feature) +{ + env->features |= (1u << feature); +} + /* CPUClass::reset() */ static void m68k_cpu_reset(CPUState *s) { @@ -48,6 +53,72 @@ static void m68k_cpu_reset(CPUState *s) tlb_flush(env, 1); } +/* CPU models */ + +static void m5206_cpu_initfn(Object *obj) +{ + M68kCPU *cpu = M68K_CPU(obj); + CPUM68KState *env = &cpu->env; + + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); +} + +static void m5208_cpu_initfn(Object *obj) +{ + M68kCPU *cpu = M68K_CPU(obj); + CPUM68KState *env = &cpu->env; + + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); + m68k_set_feature(env, M68K_FEATURE_BRAL); + m68k_set_feature(env, M68K_FEATURE_CF_EMAC); + m68k_set_feature(env, M68K_FEATURE_USP); +} + +static void cfv4e_cpu_initfn(Object *obj) +{ + M68kCPU *cpu = M68K_CPU(obj); + CPUM68KState *env = &cpu->env; + + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); + m68k_set_feature(env, M68K_FEATURE_BRAL); + m68k_set_feature(env, M68K_FEATURE_CF_FPU); + m68k_set_feature(env, M68K_FEATURE_CF_EMAC); + m68k_set_feature(env, M68K_FEATURE_USP); +} + +static void any_cpu_initfn(Object *obj) +{ + M68kCPU *cpu = M68K_CPU(obj); + CPUM68KState *env = &cpu->env; + + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); + m68k_set_feature(env, M68K_FEATURE_BRAL); + m68k_set_feature(env, M68K_FEATURE_CF_FPU); + /* MAC and EMAC are mututally exclusive, so pick EMAC. + It's mostly backwards compatible. */ + m68k_set_feature(env, M68K_FEATURE_CF_EMAC); + m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B); + m68k_set_feature(env, M68K_FEATURE_USP); + m68k_set_feature(env, M68K_FEATURE_EXT_FULL); + m68k_set_feature(env, M68K_FEATURE_WORD_INDEX); +} + +typedef struct M68kCPUInfo { + const char *name; + void (*instance_init)(Object *obj); +} M68kCPUInfo; + +static const M68kCPUInfo m68k_cpus[] = { + { .name = "m5206", .instance_init = m5206_cpu_initfn }, + { .name = "m5208", .instance_init = m5208_cpu_initfn }, + { .name = "cfv4e", .instance_init = cfv4e_cpu_initfn }, + { .name = "any", .instance_init = any_cpu_initfn }, +}; + static void m68k_cpu_initfn(Object *obj) { M68kCPU *cpu = M68K_CPU(obj); @@ -65,19 +136,35 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->reset = m68k_cpu_reset; } +static void register_cpu_type(const M68kCPUInfo *info) +{ + TypeInfo type_info = { + .name = info->name, + .parent = TYPE_M68K_CPU, + .instance_init = info->instance_init, + }; + + type_register_static(&type_info); +} + static const TypeInfo m68k_cpu_type_info = { .name = TYPE_M68K_CPU, .parent = TYPE_CPU, .instance_size = sizeof(M68kCPU), .instance_init = m68k_cpu_initfn, - .abstract = false, + .abstract = true, .class_size = sizeof(M68kCPUClass), .class_init = m68k_cpu_class_init, }; static void m68k_cpu_register_types(void) { + int i; + type_register_static(&m68k_cpu_type_info); + for (i = 0; i < ARRAY_SIZE(m68k_cpus); i++) { + register_cpu_type(&m68k_cpus[i]); + } } type_init(m68k_cpu_register_types) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index e850d53d40..f428375d7d 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -25,35 +25,50 @@ #define SIGNBIT (1u << 31) -enum m68k_cpuid { - M68K_CPUID_M5206, - M68K_CPUID_M5208, - M68K_CPUID_CFV4E, - M68K_CPUID_ANY, -}; +typedef struct M68kCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} M68kCPUListState; -typedef struct m68k_def_t m68k_def_t; +/* Sort alphabetically, except for "any". */ +static gint m68k_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a = (ObjectClass *)a; + ObjectClass *class_b = (ObjectClass *)b; + const char *name_a, *name_b; -struct m68k_def_t { - const char * name; - enum m68k_cpuid id; -}; + name_a = object_class_get_name(class_a); + name_b = object_class_get_name(class_b); + if (strcmp(name_a, "any") == 0) { + return 1; + } else if (strcmp(name_b, "any") == 0) { + return -1; + } else { + return strcasecmp(name_a, name_b); + } +} -static m68k_def_t m68k_cpu_defs[] = { - {"m5206", M68K_CPUID_M5206}, - {"m5208", M68K_CPUID_M5208}, - {"cfv4e", M68K_CPUID_CFV4E}, - {"any", M68K_CPUID_ANY}, - {NULL, 0}, -}; +static void m68k_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *c = data; + M68kCPUListState *s = user_data; + + (*s->cpu_fprintf)(s->file, "%s\n", + object_class_get_name(c)); +} void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - unsigned int i; + M68kCPUListState s = { + .file = f, + .cpu_fprintf = cpu_fprintf, + }; + GSList *list; - for (i = 0; m68k_cpu_defs[i].name; i++) { - (*cpu_fprintf)(f, "%s\n", m68k_cpu_defs[i].name); - } + list = object_class_get_list(TYPE_M68K_CPU, false); + list = g_slist_sort(list, m68k_cpu_list_compare); + g_slist_foreach(list, m68k_cpu_list_entry, &s); + g_slist_free(list); } static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n) @@ -83,66 +98,6 @@ static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) return 0; } -static void m68k_set_feature(CPUM68KState *env, int feature) -{ - env->features |= (1u << feature); -} - -static int cpu_m68k_set_model(CPUM68KState *env, const char *name) -{ - m68k_def_t *def; - - for (def = m68k_cpu_defs; def->name; def++) { - if (strcmp(def->name, name) == 0) - break; - } - if (!def->name) - return -1; - - switch (def->id) { - case M68K_CPUID_M5206: - m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); - break; - case M68K_CPUID_M5208: - m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); - m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); - m68k_set_feature(env, M68K_FEATURE_BRAL); - m68k_set_feature(env, M68K_FEATURE_CF_EMAC); - m68k_set_feature(env, M68K_FEATURE_USP); - break; - case M68K_CPUID_CFV4E: - m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); - m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); - m68k_set_feature(env, M68K_FEATURE_BRAL); - m68k_set_feature(env, M68K_FEATURE_CF_FPU); - m68k_set_feature(env, M68K_FEATURE_CF_EMAC); - m68k_set_feature(env, M68K_FEATURE_USP); - break; - case M68K_CPUID_ANY: - m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); - m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); - m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); - m68k_set_feature(env, M68K_FEATURE_BRAL); - m68k_set_feature(env, M68K_FEATURE_CF_FPU); - /* MAC and EMAC are mututally exclusive, so pick EMAC. - It's mostly backwards compatible. */ - m68k_set_feature(env, M68K_FEATURE_CF_EMAC); - m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B); - m68k_set_feature(env, M68K_FEATURE_USP); - m68k_set_feature(env, M68K_FEATURE_EXT_FULL); - m68k_set_feature(env, M68K_FEATURE_WORD_INDEX); - break; - } - - register_m68k_insns(env); - if (m68k_feature (env, M68K_FEATURE_CF_FPU)) { - gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg, - 11, "cf-fp.xml", 18); - } - /* TODO: Add [E]MAC registers. */ - return 0; -} - void cpu_state_reset(CPUM68KState *env) { cpu_reset(ENV_GET_CPU(env)); @@ -154,7 +109,10 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) CPUM68KState *env; static int inited; - cpu = M68K_CPU(object_new(TYPE_M68K_CPU)); + if (object_class_by_name(cpu_model) == NULL) { + return NULL; + } + cpu = M68K_CPU(object_new(cpu_model)); env = &cpu->env; if (!inited) { @@ -164,10 +122,12 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) env->cpu_model_str = cpu_model; - if (cpu_m68k_set_model(env, cpu_model) < 0) { - object_delete(OBJECT(cpu)); - return NULL; + register_m68k_insns(env); + if (m68k_feature(env, M68K_FEATURE_CF_FPU)) { + gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg, + 11, "cf-fp.xml", 18); } + /* TODO: Add [E]MAC registers. */ cpu_reset(ENV_GET_CPU(env)); qemu_init_vcpu(env); From 0f71a7095db6bc055bc5bb520d85ea650cca8a33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 15 Apr 2012 23:29:19 +0200 Subject: [PATCH 10/12] target-mips: QOM'ify CPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber Reviewed-by: Richard Henderson --- Makefile.target | 3 ++ target-mips/cpu-qom.h | 74 +++++++++++++++++++++++++++++++++++++++++ target-mips/cpu.c | 60 +++++++++++++++++++++++++++++++++ target-mips/cpu.h | 2 ++ target-mips/translate.c | 4 ++- 5 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 target-mips/cpu-qom.h create mode 100644 target-mips/cpu.c diff --git a/Makefile.target b/Makefile.target index e735064be7..f7b2e7145a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -98,6 +98,9 @@ libobj-$(TARGET_CRIS) += cpu.o libobj-$(TARGET_LM32) += cpu.o libobj-$(TARGET_M68K) += cpu.o libobj-$(TARGET_MICROBLAZE) += cpu.o +ifeq ($(TARGET_BASE_ARCH), mips) +libobj-y += cpu.o +endif libobj-$(TARGET_S390X) += cpu.o libobj-$(TARGET_SH4) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h new file mode 100644 index 0000000000..6e2237123a --- /dev/null +++ b/target-mips/cpu-qom.h @@ -0,0 +1,74 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ +#ifndef QEMU_MIPS_CPU_QOM_H +#define QEMU_MIPS_CPU_QOM_H + +#include "qemu/cpu.h" + +#ifdef TARGET_MIPS64 +#define TYPE_MIPS_CPU "mips64-cpu" +#else +#define TYPE_MIPS_CPU "mips-cpu" +#endif + +#define MIPS_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU) +#define MIPS_CPU(obj) \ + OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU) +#define MIPS_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU) + +/** + * MIPSCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A MIPS CPU model. + */ +typedef struct MIPSCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); +} MIPSCPUClass; + +/** + * MIPSCPU: + * @env: #CPUMIPSState + * + * A MIPS CPU. + */ +typedef struct MIPSCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUMIPSState env; +} MIPSCPU; + +static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) +{ + return MIPS_CPU(container_of(env, MIPSCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) + + +#endif diff --git a/target-mips/cpu.c b/target-mips/cpu.c new file mode 100644 index 0000000000..d573ec8be8 --- /dev/null +++ b/target-mips/cpu.c @@ -0,0 +1,60 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "cpu.h" +#include "qemu-common.h" + + +/* CPUClass::reset() */ +static void mips_cpu_reset(CPUState *s) +{ + MIPSCPU *cpu = MIPS_CPU(s); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); + CPUMIPSState *env = &cpu->env; + + mcc->parent_reset(s); + + cpu_state_reset(env); +} + +static void mips_cpu_class_init(ObjectClass *c, void *data) +{ + MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); + CPUClass *cc = CPU_CLASS(c); + + mcc->parent_reset = cc->reset; + cc->reset = mips_cpu_reset; +} + +static const TypeInfo mips_cpu_type_info = { + .name = TYPE_MIPS_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(MIPSCPU), + .abstract = false, + .class_size = sizeof(MIPSCPUClass), + .class_init = mips_cpu_class_init, +}; + +static void mips_cpu_register_types(void) +{ + type_register_static(&mips_cpu_type_info); +} + +type_init(mips_cpu_register_types) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 257c4c462b..99b416c47f 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -483,6 +483,8 @@ struct CPUMIPSState { struct QEMUTimer *timer; /* Internal timer */ }; +#include "cpu-qom.h" + #if !defined(CONFIG_USER_ONLY) int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); diff --git a/target-mips/translate.c b/target-mips/translate.c index a663b743c1..b10ec2196a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12691,13 +12691,15 @@ static void mips_tcg_init(void) CPUMIPSState *cpu_mips_init (const char *cpu_model) { + MIPSCPU *cpu; CPUMIPSState *env; const mips_def_t *def; def = cpu_mips_find_by_name(cpu_model); if (!def) return NULL; - env = g_malloc0(sizeof(CPUMIPSState)); + cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); + env = &cpu->env; env->cpu_model = def; env->cpu_model_str = cpu_model; From 5b0c40f7460a017d0322d942a6abda9e8815676b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 16 Apr 2012 02:37:56 +0200 Subject: [PATCH 11/12] target-mips: Start QOM'ifying CPU init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code not dependent on mips_def_t from cpu_mips_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber Reviewed-by: Richard Henderson --- target-mips/cpu.c | 9 +++++++++ target-mips/translate.c | 1 - 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.c b/target-mips/cpu.c index d573ec8be8..004406232b 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -34,6 +34,14 @@ static void mips_cpu_reset(CPUState *s) cpu_state_reset(env); } +static void mips_cpu_initfn(Object *obj) +{ + MIPSCPU *cpu = MIPS_CPU(obj); + CPUMIPSState *env = &cpu->env; + + cpu_exec_init(env); +} + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -47,6 +55,7 @@ static const TypeInfo mips_cpu_type_info = { .name = TYPE_MIPS_CPU, .parent = TYPE_CPU, .instance_size = sizeof(MIPSCPU), + .instance_init = mips_cpu_initfn, .abstract = false, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, diff --git a/target-mips/translate.c b/target-mips/translate.c index b10ec2196a..f5297b0392 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12703,7 +12703,6 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model) env->cpu_model = def; env->cpu_model_str = cpu_model; - cpu_exec_init(env); #ifndef CONFIG_USER_ONLY mmu_init(env, def); #endif From 894a84e632e4e71eaa3588d7ca9854bf4d9027ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 20 Feb 2012 06:28:33 +0100 Subject: [PATCH 12/12] Makefile: Simplify compilation of target-*/cpu.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All targets except for ppc now have a standalone cpu.c file. Signed-off-by: Andreas Färber --- Makefile.target | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/Makefile.target b/Makefile.target index f7b2e7145a..364aea2f5c 100644 --- a/Makefile.target +++ b/Makefile.target @@ -87,32 +87,18 @@ libobj-y += op_helper.o endif endif libobj-y += helper.o -ifeq ($(TARGET_BASE_ARCH), i386) +ifneq ($(TARGET_BASE_ARCH), ppc) libobj-y += cpu.o endif libobj-$(TARGET_SPARC64) += vis_helper.o libobj-$(CONFIG_NEED_MMU) += mmu.o libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o -libobj-$(TARGET_ARM) += cpu.o -libobj-$(TARGET_CRIS) += cpu.o -libobj-$(TARGET_LM32) += cpu.o -libobj-$(TARGET_M68K) += cpu.o -libobj-$(TARGET_MICROBLAZE) += cpu.o -ifeq ($(TARGET_BASE_ARCH), mips) -libobj-y += cpu.o -endif -libobj-$(TARGET_S390X) += cpu.o -libobj-$(TARGET_SH4) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o -libobj-y += cpu.o endif libobj-$(TARGET_SPARC) += int32_helper.o libobj-$(TARGET_SPARC64) += int64_helper.o -libobj-$(TARGET_UNICORE32) += cpu.o -libobj-$(TARGET_XTENSA) += cpu.o libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o -libobj-$(TARGET_ALPHA) += cpu.o libobj-y += disas.o libobj-$(CONFIG_TCI_DIS) += tci-dis.o