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target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers

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Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-7-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-14 18:58:36 +01:00
parent b5b63d43a0
commit 61f4e0ec0d
2 changed files with 22 additions and 0 deletions
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18
target/mips/translate.c
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@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg)
}
}
#if defined(TARGET_MIPS64)
void gen_load_gpr_hi(TCGv_i64 t, int reg)
{
if (reg == 0) {
tcg_gen_movi_i64(t, 0);
} else {
tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
}
}
void gen_store_gpr_hi(TCGv_i64 t, int reg)
{
if (reg != 0) {
tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
}
}
#endif /* TARGET_MIPS64 */
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr(int from, int to)
{

4
target/mips/translate.h
View File

@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
#if defined(TARGET_MIPS64)
void gen_load_gpr_hi(TCGv_i64 t, int reg);
void gen_store_gpr_hi(TCGv_i64 t, int reg);
#endif /* TARGET_MIPS64 */
void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);