target/riscv: Fix wrong expanding for c.fswsp
base register is no rs1 not rs2 for fsw. Signed-off-by: Kito Cheng <kito.cheng@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
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{
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{
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#ifdef TARGET_RISCV32
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#ifdef TARGET_RISCV32
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/* C.FSWSP */
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/* C.FSWSP */
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arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
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arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
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return trans_fsw(ctx, &a_fsw);
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return trans_fsw(ctx, &a_fsw);
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#else
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#else
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/* C.SDSP */
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/* C.SDSP */
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