OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

trivial patches pull request 20220629

Browse Source 
-----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmK8FmsSHGxhdXJlbnRA
 dml2aWVyLmV1AAoJEPMMOL0/L7482EkP/19M/AAUkGqIdU9Dj7H46r+LEKtrT7Xu
 jNRDDrkhVQvx42mklSB+fO/ptMKUDgxvLs4mnuZFxM7SrTOb4h5jfZzyYjk73ENQ
 YZ/TLxRtxAfRCcGwso7NGyk85mwt+sBFKZXfW6qsfc9AjDphLUOblfSieeFegz69
 BUtzbMOPSMR7e54y6azJX3gCkxLytSXYgk4otSLTrL233sT7pnwPRdxKGzCTA5vs
 fRxKb4p/R05lWepcjrL2d2lB1TabsV0kqmNkHDvubVWlgyoK3Vt/1dzD1UP7CrvF
 WghlZWmxCHrmLlBb+VSDUa22kpfv5fi/feauuug+dya+s1Mlq8HZTL8VtjUJHwLL
 92xRPeP/RfEJdoQDuMKXP9DWAAYM03HGgR37cE5NMDCyHG0XRKOJ+i2P7DQLVDjW
 QyWX6bX1WV6FovdwwMnZR9OclvKtsZnb1jlfj+G2DdKXpLliDH6DkFm8mPQTM1L7
 w53iMtK88erEc+NP6+fPbbZmySvDVUcLmcTiBceZK6Vjo4oTGNrAWP+VgjBTJaz+
 71ulkJ6vo39ZnEQOUlWrL/yW+8sQNaeO1tO67HZZ8dgTvAnPwyvKq88jSMzGCNpz
 Wpcf4yVAEvU+fP3KkEaqQqmQeK/Vc+H6044O00tcLVICkpCdN/FwRjgfZanX9CIJ
 xQjxW5mkb1Z3
 =fgtJ
 -----END PGP SIGNATURE-----

Merge tag 'trivial-branch-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging

trivial patches pull request 20220629

# -----BEGIN PGP SIGNATURE-----
#
# iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmK8FmsSHGxhdXJlbnRA
# dml2aWVyLmV1AAoJEPMMOL0/L7482EkP/19M/AAUkGqIdU9Dj7H46r+LEKtrT7Xu
# jNRDDrkhVQvx42mklSB+fO/ptMKUDgxvLs4mnuZFxM7SrTOb4h5jfZzyYjk73ENQ
# YZ/TLxRtxAfRCcGwso7NGyk85mwt+sBFKZXfW6qsfc9AjDphLUOblfSieeFegz69
# BUtzbMOPSMR7e54y6azJX3gCkxLytSXYgk4otSLTrL233sT7pnwPRdxKGzCTA5vs
# fRxKb4p/R05lWepcjrL2d2lB1TabsV0kqmNkHDvubVWlgyoK3Vt/1dzD1UP7CrvF
# WghlZWmxCHrmLlBb+VSDUa22kpfv5fi/feauuug+dya+s1Mlq8HZTL8VtjUJHwLL
# 92xRPeP/RfEJdoQDuMKXP9DWAAYM03HGgR37cE5NMDCyHG0XRKOJ+i2P7DQLVDjW
# QyWX6bX1WV6FovdwwMnZR9OclvKtsZnb1jlfj+G2DdKXpLliDH6DkFm8mPQTM1L7
# w53iMtK88erEc+NP6+fPbbZmySvDVUcLmcTiBceZK6Vjo4oTGNrAWP+VgjBTJaz+
# 71ulkJ6vo39ZnEQOUlWrL/yW+8sQNaeO1tO67HZZ8dgTvAnPwyvKq88jSMzGCNpz
# Wpcf4yVAEvU+fP3KkEaqQqmQeK/Vc+H6044O00tcLVICkpCdN/FwRjgfZanX9CIJ
# xQjxW5mkb1Z3
# =fgtJ
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 29 Jun 2022 02:37:55 PM +0530
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [undefined]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* tag 'trivial-branch-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu:
  hw/i386/xen/xen-hvm: Inline xen_piix_pci_write_config_client() and remove it
  hw/i386/xen/xen-hvm: Allow for stubbing xen_set_pci_link_route()
  hw/ide/atapi.c: Correct typos (CD-CDROM -> CD-ROM)
  common-user: Only compile the common user code if have_user is set
  hw/pci-host/i440fx: Remove unused parameter from i440fx_init()
  MAINTAINERS: Add softmmu/runstate.c to "Main loop"
  trivial typos: namesapce
  Trivial: 3 char repeat typos
  util: Return void on iova_tree_remove
  qom/object: Remove circular include dependency
  vga: avoid crash if no default vga card

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-30 04:49:40 +05:30
commit 621745c4f3
27 changed files with 47 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -2751,6 +2751,7 @@ F: softmmu/cpu-throttle.c
F: softmmu/cpu-timers.c
F: softmmu/icount.c
F: softmmu/runstate-action.c
F: softmmu/runstate.c
F: qapi/run-state.json
Read, Copy, Update (RCU)

4
common-user/meson.build
View File

@ -1,3 +1,7 @@
if not have_user
subdir_done()
endif
common_user_inc += include_directories('host/' / host_arch)
user_ss.add(files(

8
hw/9pfs/9p-xattr-user.c
View File

@ -27,7 +27,7 @@ static ssize_t mp_user_getxattr(FsContext *ctx, const char *path,
{
if (strncmp(name, "user.virtfs.", 12) == 0) {
/*
* Don't allow fetch of user.virtfs namesapce
* Don't allow fetch of user.virtfs namespace
* in case of mapped security
*/
errno = ENOATTR;
@ -49,7 +49,7 @@ static ssize_t mp_user_listxattr(FsContext *ctx, const char *path,
name_size -= 12;
} else {
/*
* Don't allow fetch of user.virtfs namesapce
* Don't allow fetch of user.virtfs namespace
* in case of mapped security
*/
return 0;
@ -74,7 +74,7 @@ static int mp_user_setxattr(FsContext *ctx, const char *path, const char *name,
{
if (strncmp(name, "user.virtfs.", 12) == 0) {
/*
* Don't allow fetch of user.virtfs namesapce
* Don't allow fetch of user.virtfs namespace
* in case of mapped security
*/
errno = EACCES;
@ -88,7 +88,7 @@ static int mp_user_removexattr(FsContext *ctx,
{
if (strncmp(name, "user.virtfs.", 12) == 0) {
/*
* Don't allow fetch of user.virtfs namesapce
* Don't allow fetch of user.virtfs namespace
* in case of mapped security
*/
errno = EACCES;

2
hw/acpi/nvdimm.c
View File

@ -476,7 +476,7 @@ struct NvdimmFuncGetLabelDataOut {
/* the size of buffer filled by QEMU. */
uint32_t len;
uint32_t func_ret_status; /* return status code. */
uint8_t out_buf[]; /* the data got via Get Namesapce Label function. */
uint8_t out_buf[]; /* the data got via Get Namespace Label function. */
} QEMU_PACKED;
typedef struct NvdimmFuncGetLabelDataOut NvdimmFuncGetLabelDataOut;
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataOut) > NVDIMM_DSM_MEMORY_SIZE);

3
hw/i386/pc_piix.c
View File

@ -82,7 +82,6 @@ static void pc_init1(MachineState *machine,
MemoryRegion *system_io = get_system_io();
PCIBus *pci_bus;
ISABus *isa_bus;
PCII440FXState *i440fx_state;
int piix3_devfn = -1;
qemu_irq smi_irq;
GSIState *gsi_state;
@ -203,7 +202,6 @@ static void pc_init1(MachineState *machine,
pci_bus = i440fx_init(host_type,
pci_type,
&i440fx_state,
system_memory, system_io, machine->ram_size,
x86ms->below_4g_mem_size,
x86ms->above_4g_mem_size,
@ -217,7 +215,6 @@ static void pc_init1(MachineState *machine,
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
} else {
pci_bus = NULL;
i440fx_state = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
&error_abort);
pcms->hpet_enabled = false;

17
hw/i386/xen/xen-hvm.c
View File

@ -15,7 +15,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@ -149,21 +148,9 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int level)
irq_num & 3, level);
}
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
int xen_set_pci_link_route(uint8_t link, uint8_t irq)
{
int i;
/* Scan for updates to PCI link routes (0x60-0x63). */
for (i = 0; i < len; i++) {
uint8_t v = (val >> (8 * i)) & 0xff;
if (v & 0x80) {
v = 0;
}
v &= 0xf;
if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
}
}
return xendevicemodel_set_pci_link_route(xen_dmod, xen_domid, link, irq);
}
int xen_is_pirq_msi(uint32_t msi_data)

4
hw/ide/atapi.c
View File

@ -318,7 +318,7 @@ static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
}
}
/* start a CD-CDROM read command */
/* start a CD-ROM read command */
static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
int sector_size)
{
@ -417,7 +417,7 @@ eot:
ide_set_inactive(s, false);
}
/* start a CD-CDROM read command with DMA */
/* start a CD-ROM read command with DMA */
/* XXX: test if DMA is available */
static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
int sector_size)

2
hw/intc/openpic.c
View File

@ -729,7 +729,7 @@ static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
}
/*
* Returns the currrent tccr value, i.e., timer value (in clocks) with
* Returns the current tccr value, i.e., timer value (in clocks) with
* appropriate TOG.
*/
static uint64_t openpic_tmr_get_timer(OpenPICTimer *tmr)

15
hw/isa/piix3.c
View File

@ -138,7 +138,20 @@ static void piix3_write_config(PCIDevice *dev,
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
xen_piix_pci_write_config_client(address, val, len);
int i;
/* Scan for updates to PCI link routes (0x60-0x63). */
for (i = 0; i < len; i++) {
uint8_t v = (val >> (8 * i)) & 0xff;
if (v & 0x80) {
v = 0;
}
v &= 0xf;
if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
}
}
piix3_write_config(dev, address, val, len);
}

2
hw/net/imx_fec.c
View File

@ -438,7 +438,7 @@ static void imx_eth_update(IMXFECState *s)
* assignment fail.
*
* To ensure that all versions of Linux work, generate ENET_INT_MAC
* interrrupts on both interrupt lines. This should be changed if and when
* interrupts on both interrupt lines. This should be changed if and when
* qemu supports IOMUX.
*/
if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &

2
hw/nvme/ctrl.c
View File

@ -76,7 +76,7 @@
* the SUBNQN field in the controller will report the NQN of the subsystem
* device. This also enables multi controller capability represented in
* Identify Controller data structure in CMIC (Controller Multi-path I/O and
* Namesapce Sharing Capabilities).
* Namespace Sharing Capabilities).
*
* - `aerl`
* The Asynchronous Event Request Limit (AERL). Indicates the maximum number

4
hw/pci-host/i440fx.c
View File

@ -238,7 +238,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
@ -264,8 +263,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_create_simple(b, 0, pci_type);
*pi440fx_state = I440FX_PCI_DEVICE(d);
f = *pi440fx_state;
f = I440FX_PCI_DEVICE(d);
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
f->ram_memory = ram_memory;

2
hw/pci/pcie_aer.c
View File

@ -323,7 +323,7 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
*/
}
/* Errro Message Received: Root Error Status register */
/* Error Message Received: Root Error Status register */
switch (msg->severity) {
case PCI_ERR_ROOT_CMD_COR_EN:
if (root_status & PCI_ERR_ROOT_COR_RCV) {

3
hw/pci/shpc.c
View File

@ -480,7 +480,8 @@ static const MemoryRegionOps shpc_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
/* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
* It's easier to suppport all sizes than worry about it. */
* It's easier to support all sizes than worry about it.
*/
.min_access_size = 1,
.max_access_size = 4,
},

2
hw/ppc/spapr_caps.c
View File

@ -553,7 +553,7 @@ static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
* instruction is a harmless no-op. It won't correctly
* implement the cache count flush *but* if we have
* count-cache-disabled in the host, that flush is
* unnnecessary. So, specifically allow this case. This
* unnecessary. So, specifically allow this case. This
* allows us to have better performance on POWER9 DD2.3,
* while still working on POWER9 DD2.2 and POWER8 host
* cpus.

2
hw/scsi/spapr_vscsi.c
View File

@ -1013,7 +1013,7 @@ static int vscsi_send_capabilities(VSCSIState *s, vscsi_req *req)
}
/*
* Current implementation does not suppport any migration or
* Current implementation does not support any migration or
* reservation capabilities. Construct the response telling the
* guest not to use them.
*/

1
include/hw/pci-host/i440fx.h
View File

@ -36,7 +36,6 @@ struct PCII440FXState {
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,

2
include/hw/xen/xen.h
View File

@ -21,8 +21,8 @@ extern enum xen_mode xen_mode;
extern bool xen_domid_restrict;
int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
int xen_set_pci_link_route(uint8_t link, uint8_t irq);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
int xen_is_pirq_msi(uint32_t msi_data);

6
include/hw/xen/xen_common.h
View File

@ -316,12 +316,6 @@ static inline int xen_set_pci_intx_level(domid_t domid, uint16_t segment,
device, intx, level);
}
static inline int xen_set_pci_link_route(domid_t domid, uint8_t link,
uint8_t irq)
{
return xendevicemodel_set_pci_link_route(xen_dmod, domid, link, irq);
}
static inline int xen_inject_msi(domid_t domid, uint64_t msi_addr,
uint32_t msi_data)
{

4
include/qemu/iova-tree.h
View File

@ -72,10 +72,8 @@ int iova_tree_insert(IOVATree *tree, const DMAMap *map);
* provided. The range does not need to be exactly what has inserted,
* all the mappings that are included in the provided range will be
* removed from the tree. Here map->translated_addr is meaningless.
*
* Return: 0 if succeeded, or <0 if error.
*/
int iova_tree_remove(IOVATree *tree, const DMAMap *map);
void iova_tree_remove(IOVATree *tree, const DMAMap *map);
/**
* iova_tree_find:

1
include/qom/object.h
View File

@ -16,7 +16,6 @@
#include "qapi/qapi-builtin-types.h"
#include "qemu/module.h"
#include "qom/object.h"
struct TypeImpl;
typedef struct TypeImpl *Type;

2
qapi/net.json
View File

@ -298,7 +298,7 @@
#
# @udp: use the udp version of l2tpv3 encapsulation
#
# @cookie64: use 64 bit coookies
# @cookie64: use 64 bit cookies
#
# @counter: have sequence counter
#

3
softmmu/vl.c
View File

@ -981,7 +981,8 @@ static void select_vgahw(const MachineClass *machine_class, const char *p)
if (vga_interface_available(t) && ti->opt_name) {
printf("%-20s %s%s\n", ti->opt_name, ti->name ?: "",
g_str_equal(ti->opt_name, def) ? " (default)" : "");
(def && g_str_equal(ti->opt_name, def)) ?
" (default)" : "");
}
}
exit(0);

3
stubs/xen-hw-stub.c
View File

@ -19,8 +19,9 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int level)
{
}
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
int xen_set_pci_link_route(uint8_t link, uint8_t irq)
{
return -1;
}
void xen_hvm_inject_msi(uint64_t addr, uint32_t data)

2
tools/virtiofsd/passthrough_ll.c
View File

@ -2319,7 +2319,7 @@ static int do_lo_create(fuse_req_t req, struct lo_inode *parent_inode,
* If security.selinux has not been remapped and selinux is enabled,
* use fscreate to set context before file creation. If not, use
* tmpfile method for regular files. Otherwise fallback to
* non-atomic method of file creation and xattr settting.
* non-atomic method of file creation and xattr setting.
*/
if (!mapped_name && lo->use_fscreate) {
err = do_create_secctx_fscreate(req, parent_inode, name, mode, fi,

2
ui/input.c
View File

@ -364,7 +364,7 @@ void qemu_input_event_send(QemuConsole *src, InputEvent *evt)
* when 'alt+print' was pressed. This flaw is now fixed and the
* 'sysrq' key serves no further purpose. We normalize it to
* 'print', so that downstream receivers of the event don't
* neeed to deal with this mistake
* need to deal with this mistake
*/
if (evt->type == INPUT_EVENT_KIND_KEY &&
evt->u.key.data->key->u.qcode.data == Q_KEY_CODE_SYSRQ) {

4
util/iova-tree.c
View File

@ -164,15 +164,13 @@ void iova_tree_foreach(IOVATree *tree, iova_tree_iterator iterator)
g_tree_foreach(tree->tree, iova_tree_traverse, iterator);
}
int iova_tree_remove(IOVATree *tree, const DMAMap *map)
void iova_tree_remove(IOVATree *tree, const DMAMap *map)
{
const DMAMap *overlap;
while ((overlap = iova_tree_find(tree, map))) {
g_tree_remove(tree->tree, overlap);
}
return IOVA_OK;
}
/**