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target-mips: Fix formatting in `mips_defs'

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Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Maciej W. Rozycki 2014-11-05 15:34:58 +00:00 committed by Leon Alrae
parent d75de74967
commit 6225a4a0e3
1 changed files with 21 additions and 19 deletions
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40
target-mips/translate_init.c
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@ -645,10 +645,11 @@ static const mips_def_t mips_defs[] =
{ {
.name = "Loongson-2E", .name = "Loongson-2E",
.CP0_PRid = 0x6302, .CP0_PRid = 0x6302,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
(0x1<<4) | (0x1<<1), (0x1<<5) | (0x1<<4) | (0x1<<1),
/* Note: Config1 is only used internally, Loongson-2E has only Config0. */ /* Note: Config1 is only used internally,
Loongson-2E has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.SYNCI_Step = 16, .SYNCI_Step = 16,
.CCRes = 2, .CCRes = 2,
@ -660,21 +661,22 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{ {
.name = "Loongson-2F", .name = "Loongson-2F",
.CP0_PRid = 0x6303, .CP0_PRid = 0x6303,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
(0x1<<4) | (0x1<<1), (0x1<<5) | (0x1<<4) | (0x1<<1),
/* Note: Config1 is only used internally, Loongson-2F has only Config0. */ /* Note: Config1 is only used internally,
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), Loongson-2F has only Config0. */
.SYNCI_Step = 16, .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CCRes = 2, .SYNCI_Step = 16,
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ .CCRes = 2,
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
.SEGBITS = 40, .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
.PABITS = 40, .SEGBITS = 40,
.insn_flags = CPU_LOONGSON2F, .PABITS = 40,
.mmu_type = MMU_TYPE_R4000, .insn_flags = CPU_LOONGSON2F,
.mmu_type = MMU_TYPE_R4000,
}, },
{ {
/* A generic CPU providing MIPS64 ASE DSP 2 features. /* A generic CPU providing MIPS64 ASE DSP 2 features.