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target/riscv: Fix checks in hmode/hmode32 

Add check for the implicit dependence between H and S

Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2022-07-18 21:09:54 +08:00 committed by Alistair Francis
parent c126f83cd6
commit 62a09b9b41
2 changed files with 7 additions and 7 deletions
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5
target/riscv/cpu.c
View File

@ -733,6 +733,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;

9
target/riscv/csr.c
View File

@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
static RISCVException hmode(CPURISCVState *env, int csrno)
{
if (riscv_has_ext(env, RVS) &&
riscv_has_ext(env, RVH)) {
if (riscv_has_ext(env, RVH)) {
/* Hypervisor extension is supported */
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (riscv_cpu_mxl(env) != MXL_RV32) {
if (!riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return RISCV_EXCP_ILLEGAL_INST;
}
return hmode(env, csrno);