hw/arm/sbsa-ref: use XHCI to replace EHCI
The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB. Hence, this uses XHCI to provide a usb controller with 64-bit DMA capablity instead of EHCI. We bump the platform version to 0.3 with this change. Although the hardware at the USB controller address changes, the firmware and Linux can both cope with this -- on an older non-XHCI-aware firmware/kernel setup the probe routine simply fails and the guest proceeds without any USB. (This isn't a loss of functionality, because the old USB controller never worked in the first place.) So we can call this a backwards-compatible change and only bump the minor version. Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn [PMM: tweaked commit message; add line to docs about what changes in platform version 0.3] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -19,7 +19,7 @@ The ``sbsa-ref`` board supports:
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- A configurable number of AArch64 CPUs
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- GIC version 3
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- System bus AHCI controller
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- System bus EHCI controller
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- System bus XHCI controller
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- CDROM and hard disc on AHCI bus
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- E1000E ethernet card on PCIe bus
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- Bochs display adapter on PCIe bus
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@ -68,3 +68,6 @@ Platform version changes:
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0.2
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GIC ITS information is present in devicetree.
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0.3
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The USB controller is an XHCI device, not EHCI
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@ -266,7 +266,7 @@ config SBSA_REF
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select PL011 # UART
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select PL031 # RTC
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select PL061 # GPIO
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select USB_EHCI_SYSBUS
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select USB_XHCI_SYSBUS
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select WDT_SBSA
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select BOCHS_DISPLAY
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@ -42,6 +42,7 @@
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#include "hw/pci-host/gpex.h"
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#include "hw/qdev-properties.h"
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#include "hw/usb.h"
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#include "hw/usb/xhci.h"
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#include "hw/char/pl011.h"
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#include "hw/watchdog/sbsa_gwdt.h"
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#include "net/net.h"
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@ -85,7 +86,7 @@ enum {
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SBSA_SECURE_UART_MM,
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SBSA_SECURE_MEM,
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SBSA_AHCI,
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SBSA_EHCI,
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SBSA_XHCI,
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};
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struct SBSAMachineState {
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@ -123,7 +124,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
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[SBSA_SMMU] = { 0x60050000, 0x00020000 },
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/* Space here reserved for more SMMUs */
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[SBSA_AHCI] = { 0x60100000, 0x00010000 },
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[SBSA_EHCI] = { 0x60110000, 0x00010000 },
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[SBSA_XHCI] = { 0x60110000, 0x00010000 },
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/* Space here reserved for other devices */
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[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
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/* 32-bit address PCIE MMIO space */
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@ -143,7 +144,7 @@ static const int sbsa_ref_irqmap[] = {
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[SBSA_SECURE_UART] = 8,
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[SBSA_SECURE_UART_MM] = 9,
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[SBSA_AHCI] = 10,
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[SBSA_EHCI] = 11,
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[SBSA_XHCI] = 11,
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[SBSA_SMMU] = 12, /* ... to 15 */
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[SBSA_GWDT_WS0] = 16,
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};
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@ -230,7 +231,7 @@ static void create_fdt(SBSAMachineState *sms)
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* fw compatibility.
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*/
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qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
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qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
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qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3);
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if (ms->numa_state->have_numa_distance) {
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int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
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@ -604,13 +605,15 @@ static void create_ahci(const SBSAMachineState *sms)
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}
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}
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static void create_ehci(const SBSAMachineState *sms)
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static void create_xhci(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_EHCI];
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hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_XHCI];
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DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
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sysbus_create_simple("platform-ehci-usb", base,
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qdev_get_gpio_in(sms->gic, irq));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
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}
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static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
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@ -832,7 +835,7 @@ static void sbsa_ref_init(MachineState *machine)
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create_ahci(sms);
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create_ehci(sms);
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create_xhci(sms);
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create_pcie(sms);
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