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target/hppa: Implement P*TLB and P*TLBE insns 

We now have all of the TLB manipulation instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2017-10-27 18:33:23 +02:00
parent 8d6ae7fb3a
commit 63300a00ab
3 changed files with 79 additions and 0 deletions
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2
target/hppa/helper.h
View File

@ -88,4 +88,6 @@ DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr)
DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr)
DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env)
#endif

37
target/hppa/mem_helper.c
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@ -277,4 +277,41 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
ent->t = extract32(reg, 29, 1);
ent->entry_valid = 1;
}
/* Purge (Insn/Data) TLB. This is explicitly page-based, and is
synchronous across all processors. */
static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
{
CPUHPPAState *env = cpu->env_ptr;
target_ulong addr = (target_ulong) data.target_ptr;
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
if (ent && ent->entry_valid) {
hppa_flush_tlb_ent(env, ent);
}
}
void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
{
CPUState *src = CPU(hppa_env_get_cpu(env));
CPUState *cpu;
run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr);
CPU_FOREACH(cpu) {
if (cpu != src) {
async_run_on_cpu(cpu, ptlb_work, data);
}
}
async_safe_run_on_cpu(src, ptlb_work, data);
}
/* Purge (Insn/Data) TLB entry. This affects an implementation-defined
number of pages/entries (we choose all), and is local to the cpu. */
void HELPER(ptlbe)(CPUHPPAState *env)
{
CPUState *src = CPU(hppa_env_get_cpu(env));
memset(env->tlb, 0, sizeof(env->tlb));
tlb_flush_by_mmuidx(src, 0xf);
}
#endif /* CONFIG_USER_ONLY */

40
target/hppa/translate.c
View File

@ -2397,6 +2397,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn,
return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C)
? DISAS_IAQ_N_STALE : DISAS_NEXT);
}
static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn,
const DisasInsn *di)
{
unsigned m = extract32(insn, 5, 1);
unsigned sp;
unsigned rx = extract32(insn, 16, 5);
unsigned rb = extract32(insn, 21, 5);
unsigned is_data = insn & 0x1000;
unsigned is_local = insn & 0x40;
TCGv_tl addr;
TCGv_reg ofs;
if (is_data) {
sp = extract32(insn, 14, 2);
} else {
sp = ~assemble_sr3(insn);
}
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false);
if (m) {
save_gpr(ctx, rb, ofs);
}
if (is_local) {
gen_helper_ptlbe(cpu_env);
} else {
gen_helper_ptlb(cpu_env, addr);
}
/* Exit TB for TLB change if mmu is enabled. */
return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C)
? DISAS_IAQ_N_STALE : DISAS_NEXT);
}
#endif /* !CONFIG_USER_ONLY */
static const DisasInsn table_mem_mgmt[] = {
@ -2420,6 +2456,10 @@ static const DisasInsn table_mem_mgmt[] = {
{ 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */
{ 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */
{ 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */
{ 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */
{ 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */
{ 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */
{ 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */
#endif
};