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Replace always_inline with inline 

We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-08-16 09:06:54 +00:00
parent facd285778
commit 636aa20056
13 changed files with 355 additions and 371 deletions
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28
hw/ppc.c
View File

@ -393,8 +393,8 @@ struct ppc_tb_t {
void *opaque;
};
static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,
int64_t tb_offset)
static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
int64_t tb_offset)
{
/* TB time in tb periods */
return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;
@ -411,7 +411,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
return tb & 0xFFFFFFFF;
}
static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -427,9 +427,8 @@ uint32_t cpu_ppc_load_tbu (CPUState *env)
return _cpu_ppc_load_tbu(env);
}
static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
int64_t *tb_offsetp,
uint64_t value)
static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
int64_t *tb_offsetp, uint64_t value)
{
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
@ -447,7 +446,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
&tb_env->tb_offset, tb | (uint64_t)value);
}
static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@ -550,8 +549,7 @@ static void cpu_ppc_tb_start (CPUState *env)
}
}
static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
uint64_t next)
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
{
ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
@ -594,14 +592,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
*/
static always_inline void cpu_ppc_decr_excp (CPUState *env)
static inline void cpu_ppc_decr_excp(CPUState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
static inline void cpu_ppc_hdecr_excp(CPUState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
@ -635,8 +633,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
(*raise_excp)(env);
}
static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
uint32_t value, int is_excp)
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@ -654,8 +652,8 @@ static void cpu_ppc_decr_cb (void *opaque)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;

2
hw/ppc4xx_devs.c
View File

@ -377,7 +377,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
return bcr;
}
static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
static inline target_phys_addr_t sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}

7
hw/ppc_prep.c
View File

@ -115,7 +115,7 @@ static void _PPC_intack_write (void *opaque,
// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
}
static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
{
uint32_t retval = 0;
@ -426,9 +426,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
return retval;
}
static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
target_phys_addr_t
addr)
static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
target_phys_addr_t addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */

7
osdep.h
View File

@ -48,12 +48,9 @@
#endif
#ifndef always_inline
#if (__GNUC__ < 3) || defined(__APPLE__)
#define always_inline inline
#else
#define always_inline __attribute__ (( always_inline )) __inline__
#if !((__GNUC__ < 3) || defined(__APPLE__))
#ifdef __OPTIMIZE__
#define inline always_inline
#define inline __attribute__ (( always_inline )) __inline__
#endif
#endif
#else

9
target-alpha/exec.h
View File

@ -39,20 +39,21 @@ register struct CPUAlphaState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static always_inline void env_to_regs(void)
static inline void env_to_regs(void)
{
}
static always_inline void regs_to_env(void)
static inline void regs_to_env(void)
{
}
static always_inline int cpu_has_work(CPUState *env)
static inline int cpu_has_work(CPUState *env)
{
return (env->interrupt_request & CPU_INTERRUPT_HARD);
}
static always_inline int cpu_halted(CPUState *env) {
static inline int cpu_halted(CPUState *env)
{
if (!env->halted)
return 0;
if (cpu_has_work(env)) {

20
target-alpha/op_helper.c
View File

@ -200,7 +200,7 @@ uint64_t helper_cttz (uint64_t arg)
return ctz64(arg);
}
static always_inline uint64_t byte_zap (uint64_t op, uint8_t mskb)
static inline uint64_t byte_zap(uint64_t op, uint8_t mskb)
{
uint64_t mask;
@ -322,7 +322,7 @@ uint64_t helper_cmpbge (uint64_t op1, uint64_t op2)
/* Floating point helpers */
/* F floating (VAX) */
static always_inline uint64_t float32_to_f (float32 fa)
static inline uint64_t float32_to_f(float32 fa)
{
uint64_t r, exp, mant, sig;
CPU_FloatU a;
@ -355,7 +355,7 @@ static always_inline uint64_t float32_to_f (float32 fa)
return r;
}
static always_inline float32 f_to_float32 (uint64_t a)
static inline float32 f_to_float32(uint64_t a)
{
uint32_t exp, mant_sig;
CPU_FloatU r;
@ -449,7 +449,7 @@ uint64_t helper_sqrtf (uint64_t t)
/* G floating (VAX) */
static always_inline uint64_t float64_to_g (float64 fa)
static inline uint64_t float64_to_g(float64 fa)
{
uint64_t r, exp, mant, sig;
CPU_DoubleU a;
@ -482,7 +482,7 @@ static always_inline uint64_t float64_to_g (float64 fa)
return r;
}
static always_inline float64 g_to_float64 (uint64_t a)
static inline float64 g_to_float64(uint64_t a)
{
uint64_t exp, mant_sig;
CPU_DoubleU r;
@ -576,7 +576,7 @@ uint64_t helper_sqrtg (uint64_t a)
/* S floating (single) */
static always_inline uint64_t float32_to_s (float32 fa)
static inline uint64_t float32_to_s(float32 fa)
{
CPU_FloatU a;
uint64_t r;
@ -589,7 +589,7 @@ static always_inline uint64_t float32_to_s (float32 fa)
return r;
}
static always_inline float32 s_to_float32 (uint64_t a)
static inline float32 s_to_float32(uint64_t a)
{
CPU_FloatU r;
r.l = ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff);
@ -660,7 +660,7 @@ uint64_t helper_sqrts (uint64_t a)
/* T floating (double) */
static always_inline float64 t_to_float64 (uint64_t a)
static inline float64 t_to_float64(uint64_t a)
{
/* Memory format is the same as float64 */
CPU_DoubleU r;
@ -668,7 +668,7 @@ static always_inline float64 t_to_float64 (uint64_t a)
return r.d;
}
static always_inline uint64_t float64_to_t (float64 fa)
static inline uint64_t float64_to_t(float64 fa)
{
/* Memory format is the same as float64 */
CPU_DoubleU r;
@ -939,7 +939,7 @@ uint64_t helper_cvtlq (uint64_t a)
return (int64_t)((int32_t)((a >> 32) | ((a >> 29) & 0x3FFFFFFF)));
}
static always_inline uint64_t __helper_cvtql (uint64_t a, int s, int v)
static inline uint64_t __helper_cvtql(uint64_t a, int s, int v)
{
uint64_t r;

90
target-alpha/translate.c
View File

@ -103,8 +103,7 @@ static void alpha_translate_init(void)
done_init = 1;
}
static always_inline void gen_excp (DisasContext *ctx,
int exception, int error_code)
static inline void gen_excp(DisasContext *ctx, int exception, int error_code)
{
TCGv_i32 tmp1, tmp2;
@ -116,12 +115,12 @@ static always_inline void gen_excp (DisasContext *ctx,
tcg_temp_free_i32(tmp1);
}
static always_inline void gen_invalid (DisasContext *ctx)
static inline void gen_invalid(DisasContext *ctx)
{
gen_excp(ctx, EXCP_OPCDEC, 0);
}
static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
@ -132,7 +131,7 @@ static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
tcg_gen_qemu_ld64(tmp, t1, flags);
@ -140,7 +139,7 @@ static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
@ -151,22 +150,23 @@ static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld32s(t0, t1, flags);
}
static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld64(t0, t1, flags);
}
static always_inline void gen_load_mem (DisasContext *ctx,
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
int ra, int rb, int32_t disp16,
int fp, int clear)
static inline void gen_load_mem(DisasContext *ctx,
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
int flags),
int ra, int rb, int32_t disp16, int fp,
int clear)
{
TCGv addr;
@ -190,7 +190,7 @@ static always_inline void gen_load_mem (DisasContext *ctx,
tcg_temp_free(addr);
}
static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
@ -201,7 +201,7 @@ static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
tcg_temp_free_i32(tmp32);
}
static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
gen_helper_g_to_memory(tmp, t0);
@ -209,7 +209,7 @@ static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
@ -220,7 +220,7 @@ static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
tcg_temp_free_i32(tmp32);
}
static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
@ -236,7 +236,7 @@ static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
tcg_gen_movi_i64(cpu_lock, -1);
}
static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
@ -252,10 +252,11 @@ static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
tcg_gen_movi_i64(cpu_lock, -1);
}
static always_inline void gen_store_mem (DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
int ra, int rb, int32_t disp16,
int fp, int clear, int local)
static inline void gen_store_mem(DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
int flags),
int ra, int rb, int32_t disp16, int fp,
int clear, int local)
{
TCGv addr;
if (local)
@ -288,9 +289,8 @@ static always_inline void gen_store_mem (DisasContext *ctx,
tcg_temp_free(addr);
}
static always_inline void gen_bcond (DisasContext *ctx,
TCGCond cond,
int ra, int32_t disp, int mask)
static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
int32_t disp, int mask)
{
int l1, l2;
@ -317,8 +317,8 @@ static always_inline void gen_bcond (DisasContext *ctx,
gen_set_label(l2);
}
static always_inline void gen_fbcond (DisasContext *ctx, int opc,
int ra, int32_t disp16)
static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
int32_t disp16)
{
int l1, l2;
TCGv tmp;
@ -363,9 +363,8 @@ static always_inline void gen_fbcond (DisasContext *ctx, int opc,
gen_set_label(l2);
}
static always_inline void gen_cmov (TCGCond inv_cond,
int ra, int rb, int rc,
int islit, uint8_t lit, int mask)
static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc,
int islit, uint8_t lit, int mask)
{
int l1;
@ -397,7 +396,7 @@ static always_inline void gen_cmov (TCGCond inv_cond,
}
#define FARITH2(name) \
static always_inline void glue(gen_f, name)(int rb, int rc) \
static inline void glue(gen_f, name)(int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
@ -429,7 +428,7 @@ FARITH2(cvtqlv)
FARITH2(cvtqlsv)
#define FARITH3(name) \
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
@ -480,7 +479,7 @@ FARITH3(cpysn)
FARITH3(cpyse)
#define FCMOV(name) \
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
int l1; \
TCGv tmp; \
@ -512,9 +511,8 @@ FCMOV(cmpfle)
FCMOV(cmpfgt)
/* EXTWH, EXTWH, EXTLH, EXTQH */
static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
int ra, int rb, int rc,
int islit, uint8_t lit)
static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
@ -543,9 +541,8 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
}
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
int ra, int rb, int rc,
int islit, uint8_t lit)
static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
@ -568,8 +565,8 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
/* Code to call arith3 helpers */
#define ARITH3(name) \
static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
int islit, uint8_t lit) \
static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
uint8_t lit) \
{ \
if (unlikely(rc == 31)) \
return; \
@ -617,9 +614,8 @@ ARITH3(umulh)
ARITH3(mullv)
ARITH3(mulqv)
static always_inline void gen_cmp(TCGCond cond,
int ra, int rb, int rc,
int islit, uint8_t lit)
static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit,
uint8_t lit)
{
int l1, l2;
TCGv tmp;
@ -647,7 +643,7 @@ static always_inline void gen_cmp(TCGCond cond,
gen_set_label(l2);
}
static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
static inline int translate_one(DisasContext *ctx, uint32_t insn)
{
uint32_t palcode;
int32_t disp21, disp16, disp12;
@ -2336,9 +2332,9 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
return ret;
}
static always_inline void gen_intermediate_code_internal (CPUState *env,
TranslationBlock *tb,
int search_pc)
static inline void gen_intermediate_code_internal(CPUState *env,
TranslationBlock *tb,
int search_pc)
{
#if defined ALPHA_DEBUG_DISAS
static int insn_count;

2
target-ppc/cpu.h
View File

@ -781,7 +781,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
#endif
#endif
static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{
uint64_t gprv;

8
target-ppc/exec.h
View File

@ -35,21 +35,21 @@ register struct CPUPPCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static always_inline void env_to_regs (void)
static inline void env_to_regs(void)
{
}
static always_inline void regs_to_env (void)
static inline void regs_to_env(void)
{
}
static always_inline int cpu_has_work(CPUState *env)
static inline int cpu_has_work(CPUState *env)
{
return (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD));
}
static always_inline int cpu_halted (CPUState *env)
static inline int cpu_halted(CPUState *env)
{
if (!env->halted)
return 0;

145
target-ppc/helper.c
View File

@ -104,23 +104,23 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
#else
/* Common routines used by software and hardware TLBs emulation */
static always_inline int pte_is_valid (target_ulong pte0)
static inline int pte_is_valid(target_ulong pte0)
{
return pte0 & 0x80000000 ? 1 : 0;
}
static always_inline void pte_invalidate (target_ulong *pte0)
static inline void pte_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x80000000;
}
#if defined(TARGET_PPC64)
static always_inline int pte64_is_valid (target_ulong pte0)
static inline int pte64_is_valid(target_ulong pte0)
{
return pte0 & 0x0000000000000001ULL ? 1 : 0;
}
static always_inline void pte64_invalidate (target_ulong *pte0)
static inline void pte64_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x0000000000000001ULL;
}
@ -133,7 +133,7 @@ static always_inline void pte64_invalidate (target_ulong *pte0)
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
#endif
static always_inline int pp_check (int key, int pp, int nx)
static inline int pp_check(int key, int pp, int nx)
{
int access;
@ -173,7 +173,7 @@ static always_inline int pp_check (int key, int pp, int nx)
return access;
}
static always_inline int check_prot (int prot, int rw, int access_type)
static inline int check_prot(int prot, int rw, int access_type)
{
int ret;
@ -197,9 +197,8 @@ static always_inline int check_prot (int prot, int rw, int access_type)
return ret;
}
static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
target_ulong pte0, target_ulong pte1,
int h, int rw, int type)
static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
target_ulong pte1, int h, int rw, int type)
{
target_ulong ptem, mmask;
int access, ret, pteh, ptev, pp;
@ -260,24 +259,22 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
return ret;
}
static always_inline int pte32_check (mmu_ctx_t *ctx,
target_ulong pte0, target_ulong pte1,
int h, int rw, int type)
static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
}
#if defined(TARGET_PPC64)
static always_inline int pte64_check (mmu_ctx_t *ctx,
target_ulong pte0, target_ulong pte1,
int h, int rw, int type)
static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
}
#endif
static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
int ret, int rw)
static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
int ret, int rw)
{
int store = 0;
@ -302,8 +299,8 @@ static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
}
/* Software driven TLB helpers */
static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
int way, int is_code)
static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
int is_code)
{
int nr;
@ -318,7 +315,7 @@ static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
return nr;
}
static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
{
ppc6xx_tlb_t *tlb;
int nr, max;
@ -335,10 +332,9 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
tlb_flush(env, 1);
}
static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
target_ulong eaddr,
int is_code,
int match_epn)
static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
target_ulong eaddr,
int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
ppc6xx_tlb_t *tlb;
@ -361,9 +357,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
#endif
}
static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
target_ulong eaddr,
int is_code)
static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
target_ulong eaddr, int is_code)
{
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
}
@ -387,9 +382,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
env->last_way = way;
}
static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw,
int access_type)
static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int access_type)
{
ppc6xx_tlb_t *tlb;
int nr, best, way;
@ -452,9 +446,9 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
}
/* Perform BAT hit & translation */
static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
int *validp, int *protp,
target_ulong *BATu, target_ulong *BATl)
static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
int *protp, target_ulong *BATu,
target_ulong *BATl)
{
target_ulong bl;
int pp, valid, prot;
@ -477,10 +471,9 @@ static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
*protp = prot;
}
static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
int *validp, int *protp,
target_ulong *BATu,
target_ulong *BATl)
static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
int *validp, int *protp,
target_ulong *BATu, target_ulong *BATl)
{
target_ulong bl;
int key, pp, valid, prot;
@ -503,8 +496,8 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
*protp = prot;
}
static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
target_ulong virtual, int rw, int type)
static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong base, BEPIl, BEPIu, bl;
@ -579,9 +572,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
}
/* PTE table lookup */
static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
int rw, int type,
int target_page_bits)
static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
int type, int target_page_bits)
{
target_ulong base, pte0, pte1;
int i, good = -1;
@ -664,23 +656,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
return ret;
}
static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw,
int type, int target_page_bits)
static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
int target_page_bits)
{
return _find_pte(ctx, 0, h, rw, type, target_page_bits);
}
#if defined(TARGET_PPC64)
static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw,
int type, int target_page_bits)
static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
int target_page_bits)
{
return _find_pte(ctx, 1, h, rw, type, target_page_bits);
}
#endif
static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
int h, int rw, int type,
int target_page_bits)
static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
int type, int target_page_bits)
{
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64)
@ -721,20 +712,19 @@ static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
entry->tmp = slb->tmp;
}
static always_inline int slb_is_valid (ppc_slb_t *slb)
static inline int slb_is_valid(ppc_slb_t *slb)
{
return (int)(slb->tmp64 & 0x0000000008000000ULL);
}
static always_inline void slb_invalidate (ppc_slb_t *slb)
static inline void slb_invalidate(ppc_slb_t *slb)
{
slb->tmp64 &= ~0x0000000008000000ULL;
}
static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
target_ulong *vsid,
target_ulong *page_mask, int *attr,
int *target_page_bits)
static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
target_ulong *vsid, target_ulong *page_mask,
int *attr, int *target_page_bits)
{
target_ulong mask;
int n, ret;
@ -868,16 +858,16 @@ void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
#endif /* defined(TARGET_PPC64) */
/* Perform segment based translation */
static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
int sdr_sh,
target_phys_addr_t hash,
target_phys_addr_t mask)
static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
int sdr_sh,
target_phys_addr_t hash,
target_phys_addr_t mask)
{
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
}
static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
@ -1063,10 +1053,10 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
}
/* Generic TLB check function for embedded PowerPC implementations */
static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddrp,
target_ulong address,
uint32_t pid, int ext, int i)
static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddrp,
target_ulong address, uint32_t pid, int ext,
int i)
{
target_ulong mask;
@ -1117,7 +1107,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
}
/* Helpers specific to PowerPC 40x implementations */
static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
{
ppcemb_tlb_t *tlb;
int i;
@ -1129,9 +1119,8 @@ static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
tlb_flush(env, 1);
}
static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
target_ulong eaddr,
uint32_t pid)
static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
@ -1270,8 +1259,8 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
return ret;
}
static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw)
static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw)
{
int in_plb, ret;
@ -1674,9 +1663,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
/*****************************************************************************/
/* BATs management */
#if !defined(FLUSH_ALL_TLBS)
static always_inline void do_invalidate_BAT (CPUPPCState *env,
target_ulong BATu,
target_ulong mask)
static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
target_ulong mask)
{
target_ulong base, end, page;
@ -1690,8 +1678,8 @@ static always_inline void do_invalidate_BAT (CPUPPCState *env,
}
#endif
static always_inline void dump_store_bat (CPUPPCState *env, char ID,
int ul, int nr, target_ulong value)
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
target_ulong value)
{
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
@ -2046,7 +2034,7 @@ void ppc_hw_interrupt (CPUState *env)
env->error_code = 0;
}
#else /* defined (CONFIG_USER_ONLY) */
static always_inline void dump_syscall (CPUState *env)
static inline void dump_syscall(CPUState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
" r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
@ -2057,8 +2045,7 @@ static always_inline void dump_syscall (CPUState *env)
/* Note that this function should be greatly optimized
* when called with a constant excp, from ppc_hw_interrupt
*/
static always_inline void powerpc_excp (CPUState *env,
int excp_model, int excp)
static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;

10
target-ppc/helper_regs.h
View File

@ -21,7 +21,7 @@
#define __HELPER_REGS_H__
/* Swap temporary saved registers with GPRs */
static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
{
target_ulong tmp;
@ -39,7 +39,7 @@ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
env->tgpr[3] = tmp;
}
static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
static inline void hreg_compute_mem_idx(CPUPPCState *env)
{
/* Precompute MMU index */
if (msr_pr == 0 && msr_hv != 0) {
@ -49,7 +49,7 @@ static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
}
}
static always_inline void hreg_compute_hflags (CPUPPCState *env)
static inline void hreg_compute_hflags(CPUPPCState *env)
{
target_ulong hflags_mask;
@ -64,8 +64,8 @@ static always_inline void hreg_compute_hflags (CPUPPCState *env)
env->hflags |= env->hflags_nmsr;
}
static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value,
int alter_hv)
static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
int alter_hv)
{
int excp;

80
target-ppc/op_helper.c
View File

@ -239,7 +239,7 @@ void helper_store_601_batu (uint32_t nr, target_ulong val)
/*****************************************************************************/
/* Memory load and stores */
static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
static inline target_ulong addr_add(target_ulong addr, target_long arg)
{
#if defined(TARGET_PPC64)
if (!msr_sf)
@ -532,7 +532,7 @@ uint32_t helper_float64_to_float32(uint64_t arg)
return f.l;
}
static always_inline int isden (float64 d)
static inline int isden(float64 d)
{
CPU_DoubleU u;
@ -594,7 +594,7 @@ uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
}
/* Floating-point invalid operations exception */
static always_inline uint64_t fload_invalid_op_excp (int op)
static inline uint64_t fload_invalid_op_excp(int op)
{
uint64_t ret = 0;
int ve;
@ -675,7 +675,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op)
return ret;
}
static always_inline void float_zero_divide_excp (void)
static inline void float_zero_divide_excp(void)
{
env->fpscr |= 1 << FPSCR_ZX;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
@ -691,7 +691,7 @@ static always_inline void float_zero_divide_excp (void)
}
}
static always_inline void float_overflow_excp (void)
static inline void float_overflow_excp(void)
{
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
@ -709,7 +709,7 @@ static always_inline void float_overflow_excp (void)
}
}
static always_inline void float_underflow_excp (void)
static inline void float_underflow_excp(void)
{
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
@ -724,7 +724,7 @@ static always_inline void float_underflow_excp (void)
}
}
static always_inline void float_inexact_excp (void)
static inline void float_inexact_excp(void)
{
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
@ -738,7 +738,7 @@ static always_inline void float_inexact_excp (void)
}
}
static always_inline void fpscr_set_rounding_mode (void)
static inline void fpscr_set_rounding_mode(void)
{
int rnd_type;
@ -1199,7 +1199,7 @@ uint64_t helper_fctidz (uint64_t arg)
#endif
static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
static inline uint64_t do_fri(uint64_t arg, int rounding_mode)
{
CPU_DoubleU farg;
farg.ll = arg;
@ -1614,8 +1614,8 @@ void helper_store_msr (target_ulong val)
}
}
static always_inline void do_rfi (target_ulong nip, target_ulong msr,
target_ulong msrm, int keep_msrh)
static inline void do_rfi(target_ulong nip, target_ulong msr,
target_ulong msrm, int keep_msrh)
{
#if defined(TARGET_PPC64)
if (msr & (1ULL << MSR_SF)) {
@ -1956,7 +1956,7 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
/* Saturating arithmetic helpers. */
#define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
static always_inline to_type cvt##from##to (from_type x, int *sat) \
static inline to_type cvt##from##to(from_type x, int *sat) \
{ \
to_type r; \
if (use_min && x < min) { \
@ -1975,7 +1975,7 @@ SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1)
SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1)
/* Work around gcc problems with the macro version */
static always_inline uint8_t cvtuhub(uint16_t x, int *sat)
static inline uint8_t cvtuhub(uint16_t x, int *sat)
{
uint8_t r;
@ -2243,8 +2243,8 @@ VCMPFP(gtfp, ==, float_relation_greater)
#undef VCMPFP_DO
#undef VCMPFP
static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b, int record)
static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
int record)
{
int i;
int all_in = 0;
@ -3063,12 +3063,12 @@ static uint8_t hbrev[16] = {
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
};
static always_inline uint8_t byte_reverse (uint8_t val)
static inline uint8_t byte_reverse(uint8_t val)
{
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
}
static always_inline uint32_t word_reverse (uint32_t val)
static inline uint32_t word_reverse(uint32_t val)
{
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
@ -3100,7 +3100,7 @@ uint32_t helper_cntlzw32 (uint32_t val)
}
/* Single-precision floating-point conversions */
static always_inline uint32_t efscfsi (uint32_t val)
static inline uint32_t efscfsi(uint32_t val)
{
CPU_FloatU u;
@ -3109,7 +3109,7 @@ static always_inline uint32_t efscfsi (uint32_t val)
return u.l;
}
static always_inline uint32_t efscfui (uint32_t val)
static inline uint32_t efscfui(uint32_t val)
{
CPU_FloatU u;
@ -3118,7 +3118,7 @@ static always_inline uint32_t efscfui (uint32_t val)
return u.l;
}
static always_inline int32_t efsctsi (uint32_t val)
static inline int32_t efsctsi(uint32_t val)
{
CPU_FloatU u;
@ -3130,7 +3130,7 @@ static always_inline int32_t efsctsi (uint32_t val)
return float32_to_int32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctui (uint32_t val)
static inline uint32_t efsctui(uint32_t val)
{
CPU_FloatU u;
@ -3142,7 +3142,7 @@ static always_inline uint32_t efsctui (uint32_t val)
return float32_to_uint32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctsiz (uint32_t val)
static inline uint32_t efsctsiz(uint32_t val)
{
CPU_FloatU u;
@ -3154,7 +3154,7 @@ static always_inline uint32_t efsctsiz (uint32_t val)
return float32_to_int32_round_to_zero(u.f, &env->vec_status);
}
static always_inline uint32_t efsctuiz (uint32_t val)
static inline uint32_t efsctuiz(uint32_t val)
{
CPU_FloatU u;
@ -3166,7 +3166,7 @@ static always_inline uint32_t efsctuiz (uint32_t val)
return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
}
static always_inline uint32_t efscfsf (uint32_t val)
static inline uint32_t efscfsf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@ -3178,7 +3178,7 @@ static always_inline uint32_t efscfsf (uint32_t val)
return u.l;
}
static always_inline uint32_t efscfuf (uint32_t val)
static inline uint32_t efscfuf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@ -3190,7 +3190,7 @@ static always_inline uint32_t efscfuf (uint32_t val)
return u.l;
}
static always_inline uint32_t efsctsf (uint32_t val)
static inline uint32_t efsctsf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@ -3205,7 +3205,7 @@ static always_inline uint32_t efsctsf (uint32_t val)
return float32_to_int32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctuf (uint32_t val)
static inline uint32_t efsctuf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@ -3274,7 +3274,7 @@ HELPER_SPE_VECTOR_CONV(fsctsf);
HELPER_SPE_VECTOR_CONV(fsctuf);
/* Single-precision floating-point arithmetic */
static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
static inline uint32_t efsadd(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3283,7 +3283,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
return u1.l;
}
static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
static inline uint32_t efssub(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3292,7 +3292,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
return u1.l;
}
static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
static inline uint32_t efsmul(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3301,7 +3301,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
return u1.l;
}
static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
static inline uint32_t efsdiv(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3340,7 +3340,7 @@ HELPER_SPE_VECTOR_ARITH(fsmul);
HELPER_SPE_VECTOR_ARITH(fsdiv);
/* Single-precision floating-point comparisons */
static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
static inline uint32_t efststlt(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3348,7 +3348,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
static inline uint32_t efststgt(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3356,7 +3356,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
}
static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
static inline uint32_t efststeq(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@ -3364,19 +3364,19 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
static inline uint32_t efscmplt(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststlt(op1, op2);
}
static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
static inline uint32_t efscmpgt(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststgt(op1, op2);
}
static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
static inline uint32_t efscmpeq(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststeq(op1, op2);
@ -3400,7 +3400,7 @@ HELPER_SINGLE_SPE_CMP(fscmpgt);
/* efscmpeq */
HELPER_SINGLE_SPE_CMP(fscmpeq);
static always_inline uint32_t evcmp_merge (int t0, int t1)
static inline uint32_t evcmp_merge(int t0, int t1)
{
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
}
@ -3850,12 +3850,12 @@ void helper_74xx_tlbi (target_ulong EPN)
do_74xx_tlb(EPN, 1);
}
static always_inline target_ulong booke_tlb_to_page_size (int size)
static inline target_ulong booke_tlb_to_page_size(int size)
{
return 1024 << (2 * size);
}
static always_inline int booke_page_size_to_tlb (target_ulong page_size)
static inline int booke_page_size_to_tlb(target_ulong page_size)
{
int size;

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target-ppc/translate.c
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