tcg/i386: Use SHLX/SHRX/SARX instructions
These three-operand shift instructions do not require the shift count to be placed into ECX. This reduces the number of mov insns required, with the mere addition of a new register constraint. Don't attempt to get rid of the matching constraint, as that's impossible to manipulate with just a new constraint. In addition, constant shifts still need the matching constraint. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
9d2eec202f
commit
6399ab3325
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@ -133,6 +133,12 @@ static bool have_movbe;
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it there. Therefore we always define the variable. */
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bool have_bmi1;
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#if defined(CONFIG_CPUID_H) && defined(bit_BMI2)
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static bool have_bmi2;
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#else
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# define have_bmi2 0
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#endif
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type,
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@ -175,6 +181,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
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break;
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case 'c':
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case_c:
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
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break;
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@ -203,6 +210,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set32(ct->u.regs, 0, 0xf);
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break;
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case 'r':
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case_r:
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ct->ct |= TCG_CT_REG;
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_regset_set32(ct->u.regs, 0, 0xffff);
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@ -210,6 +218,13 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set32(ct->u.regs, 0, 0xff);
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}
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break;
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case 'C':
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/* With SHRX et al, we need not use ECX as shift count register. */
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if (have_bmi2) {
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goto case_r;
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} else {
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goto case_c;
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}
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/* qemu_ld/st address constraint */
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case 'L':
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@ -283,6 +298,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
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# define P_REXB_RM 0
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# define P_GS 0
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#endif
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#define P_SIMDF3 0x10000 /* 0xf3 opcode prefix */
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#define P_SIMDF2 0x20000 /* 0xf2 opcode prefix */
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#define OPC_ARITH_EvIz (0x81)
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#define OPC_ARITH_EvIb (0x83)
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@ -325,6 +342,9 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define OPC_SHIFT_1 (0xd1)
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#define OPC_SHIFT_Ib (0xc1)
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#define OPC_SHIFT_cl (0xd3)
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#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3)
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#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
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#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
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#define OPC_TESTL (0x85)
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#define OPC_XCHG_ax_r32 (0x90)
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@ -493,7 +513,14 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
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tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
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}
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tmp |= (opc & P_DATA16 ? 1 : 0); /* VEX.pp */
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/* VEX.pp */
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if (opc & P_DATA16) {
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tmp |= 1; /* 0x66 */
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} else if (opc & P_SIMDF3) {
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tmp |= 2; /* 0xf3 */
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} else if (opc & P_SIMDF2) {
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tmp |= 3; /* 0xf2 */
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}
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tmp |= (~v & 15) << 3; /* VEX.vvvv */
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tcg_out8(s, tmp);
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tcg_out8(s, opc);
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@ -1689,7 +1716,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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{
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int c, rexw = 0;
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int c, vexop, rexw = 0;
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#if TCG_TARGET_REG_BITS == 64
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# define OP_32_64(x) \
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@ -1860,19 +1887,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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OP_32_64(shl):
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c = SHIFT_SHL;
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goto gen_shift;
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vexop = OPC_SHLX;
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goto gen_shift_maybe_vex;
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OP_32_64(shr):
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c = SHIFT_SHR;
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goto gen_shift;
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vexop = OPC_SHRX;
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goto gen_shift_maybe_vex;
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OP_32_64(sar):
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c = SHIFT_SAR;
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goto gen_shift;
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vexop = OPC_SARX;
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goto gen_shift_maybe_vex;
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OP_32_64(rotl):
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c = SHIFT_ROL;
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goto gen_shift;
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OP_32_64(rotr):
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c = SHIFT_ROR;
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goto gen_shift;
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gen_shift_maybe_vex:
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if (have_bmi2 && !const_args[2]) {
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tcg_out_vex_modrm(s, vexop + rexw, args[0], args[2], args[1]);
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break;
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}
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/* FALLTHRU */
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gen_shift:
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if (const_args[2]) {
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tcg_out_shifti(s, c + rexw, args[0], args[2]);
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@ -2065,9 +2101,9 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_xor_i32, { "r", "0", "ri" } },
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{ INDEX_op_andc_i32, { "r", "r", "ri" } },
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{ INDEX_op_shl_i32, { "r", "0", "ci" } },
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{ INDEX_op_shr_i32, { "r", "0", "ci" } },
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{ INDEX_op_sar_i32, { "r", "0", "ci" } },
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{ INDEX_op_shl_i32, { "r", "0", "Ci" } },
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{ INDEX_op_shr_i32, { "r", "0", "Ci" } },
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{ INDEX_op_sar_i32, { "r", "0", "Ci" } },
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{ INDEX_op_rotl_i32, { "r", "0", "ci" } },
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{ INDEX_op_rotr_i32, { "r", "0", "ci" } },
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@ -2123,9 +2159,9 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_xor_i64, { "r", "0", "re" } },
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{ INDEX_op_andc_i64, { "r", "r", "rI" } },
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{ INDEX_op_shl_i64, { "r", "0", "ci" } },
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{ INDEX_op_shr_i64, { "r", "0", "ci" } },
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{ INDEX_op_sar_i64, { "r", "0", "ci" } },
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{ INDEX_op_shl_i64, { "r", "0", "Ci" } },
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{ INDEX_op_shr_i64, { "r", "0", "Ci" } },
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{ INDEX_op_sar_i64, { "r", "0", "Ci" } },
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{ INDEX_op_rotl_i64, { "r", "0", "ci" } },
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{ INDEX_op_rotr_i64, { "r", "0", "ci" } },
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@ -2282,6 +2318,9 @@ static void tcg_target_init(TCGContext *s)
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__cpuid_count(7, 0, a, b, c, d);
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#ifdef bit_BMI
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have_bmi1 = (b & bit_BMI) != 0;
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#endif
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#ifndef have_bmi2
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have_bmi2 = (b & bit_BMI2) != 0;
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#endif
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}
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