target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate
A 32-bit rotate insn is more common on hosts than a deposit insn, and if the host has neither the result is truely horrific. At the same time, tidy up the temporaries within these functions, drop the over-use of "likely", drop some checks for identity that will also be checked by tcg-op.c functions, and special case mask without rotate within rlwinm. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson
David Gibson
parent
24f9cd951d
commit
63ae0915f8
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@ -1610,141 +1610,109 @@ static void gen_cntlzd(DisasContext *ctx)
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/* rlwimi & rlwimi. */
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static void gen_rlwimi(DisasContext *ctx)
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{
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uint32_t mb, me, sh;
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TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
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TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
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uint32_t sh = SH(ctx->opcode);
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uint32_t mb = MB(ctx->opcode);
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uint32_t me = ME(ctx->opcode);
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mb = MB(ctx->opcode);
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me = ME(ctx->opcode);
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sh = SH(ctx->opcode);
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if (likely(sh == (31-me) && mb <= me)) {
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tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
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if (sh == (31-me) && mb <= me) {
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tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
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} else {
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target_ulong mask;
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TCGv_i32 t0;
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TCGv t1;
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TCGv t0 = tcg_temp_new();
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#if defined(TARGET_PPC64)
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tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], 32, 32);
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tcg_gen_rotli_i64(t0, t0, sh);
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#else
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tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
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#endif
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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mask = MASK(mb, me);
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new();
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tcg_gen_andi_tl(t0, t0, mask);
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tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
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tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
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tcg_temp_free(t0);
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tcg_gen_trunc_tl_i32(t0, t_rs);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_extu_i32_tl(t1, t0);
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tcg_temp_free_i32(t0);
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tcg_gen_andi_tl(t1, t1, mask);
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tcg_gen_andi_tl(t_ra, t_ra, ~mask);
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tcg_gen_or_tl(t_ra, t_ra, t1);
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tcg_temp_free(t1);
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}
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, t_ra);
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}
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}
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/* rlwinm & rlwinm. */
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static void gen_rlwinm(DisasContext *ctx)
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{
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uint32_t mb, me, sh;
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TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
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TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
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uint32_t sh = SH(ctx->opcode);
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uint32_t mb = MB(ctx->opcode);
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uint32_t me = ME(ctx->opcode);
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sh = SH(ctx->opcode);
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mb = MB(ctx->opcode);
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me = ME(ctx->opcode);
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if (likely(mb == 0 && me == (31 - sh))) {
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if (likely(sh == 0)) {
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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} else {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_shli_tl(t0, t0, sh);
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
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tcg_temp_free(t0);
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}
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} else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
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TCGv t0 = tcg_temp_new();
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tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_shri_tl(t0, t0, mb);
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
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tcg_temp_free(t0);
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} else if (likely(mb == 0 && me == 31)) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
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tcg_temp_free_i32(t0);
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if (mb == 0 && me == (31 - sh)) {
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tcg_gen_shli_tl(t_ra, t_rs, sh);
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tcg_gen_ext32u_tl(t_ra, t_ra);
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} else if (sh != 0 && me == 31 && sh == (32 - mb)) {
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tcg_gen_ext32u_tl(t_ra, t_rs);
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tcg_gen_shri_tl(t_ra, t_ra, mb);
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} else {
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TCGv t0 = tcg_temp_new();
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#if defined(TARGET_PPC64)
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tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], 32, 32);
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tcg_gen_rotli_i64(t0, t0, sh);
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#else
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tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
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#endif
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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tcg_temp_free(t0);
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if (sh == 0) {
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tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
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} else {
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TCGv_i32 t0 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rs);
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tcg_gen_rotli_i32(t0, t0, sh);
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tcg_gen_andi_i32(t0, t0, MASK(mb, me));
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tcg_gen_extu_i32_tl(t_ra, t0);
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tcg_temp_free_i32(t0);
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}
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, t_ra);
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}
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* rlwnm & rlwnm. */
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static void gen_rlwnm(DisasContext *ctx)
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{
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uint32_t mb, me;
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mb = MB(ctx->opcode);
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me = ME(ctx->opcode);
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TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
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TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
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TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
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uint32_t mb = MB(ctx->opcode);
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uint32_t me = ME(ctx->opcode);
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TCGv_i32 t0, t1;
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if (likely(mb == 0 && me == 31)) {
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_andi_i32(t0, t0, 0x1f);
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tcg_gen_rotl_i32(t1, t1, t0);
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tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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} else {
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TCGv t0;
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#if defined(TARGET_PPC64)
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TCGv t1;
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mb += 32;
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me += 32;
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#endif
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t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
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#if defined(TARGET_PPC64)
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t1 = tcg_temp_new_i64();
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tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], 32, 32);
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tcg_gen_rotl_i64(t0, t1, t0);
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tcg_temp_free_i64(t1);
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#else
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tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
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#endif
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if (unlikely(mb != 0 || me != 31)) {
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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} else {
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tcg_gen_andi_tl(t0, t0, MASK(32, 63));
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
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}
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tcg_temp_free(t0);
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, t_rb);
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tcg_gen_trunc_tl_i32(t1, t_rs);
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tcg_gen_andi_i32(t0, t0, 0x1f);
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tcg_gen_rotl_i32(t1, t1, t0);
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tcg_temp_free_i32(t0);
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tcg_gen_andi_i32(t1, t1, MASK(mb, me));
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tcg_gen_extu_i32_tl(t_ra, t1);
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tcg_temp_free_i32(t1);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, t_ra);
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}
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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#if defined(TARGET_PPC64)
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