OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

tests/tcg/ppc64le: emit bcdsub with .long when needed

Browse Source 
Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time
to detect the toolchain support to the bcdsub instruction. LLVM/Clang
supports this flag since version 3.6[2], but the instruction and related
builtins were only added in LLVM 14[3]. In the absence of other means to
detect this support at config-time, we resort to __has_builtin to
identify the presence of __builtin_bcdsub at compile-time. If the
builtin is not available, the instruction is emitted with a ".long".

[1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html
[2] 59eb767e11
[3] c933c2eb33

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-05 07:16:46 +01:00 committed by Cédric Le Goater
parent 8189cb8507
commit 63c2b746be
1 changed files with 41 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
tests/tcg/ppc64le/bcdsub.c
View File

@ -9,37 +9,48 @@
#define CRF_SO (1 << 0)
#define UNDEF 0
/*
* Use GPR pairs to load the VSR values and place the resulting VSR and CR6 in
* th, tl, and cr. Note that we avoid newer instructions (e.g., mtvsrdd/mfvsrld)
* so we can run this test on POWER8 machines.
*/
#define BCDSUB(AH, AL, BH, BL, PS) \
asm ("mtvsrd 32, %3\n\t" \
"mtvsrd 33, %4\n\t" \
"xxmrghd 32, 32, 33\n\t" \
"mtvsrd 33, %5\n\t" \
"mtvsrd 34, %6\n\t" \
"xxmrghd 33, 33, 34\n\t" \
"bcdsub. 0, 0, 1, %7\n\t" \
"mfocrf %0, 0b10\n\t" \
"mfvsrd %1, 32\n\t" \
"xxswapd 32, 32\n\t" \
"mfvsrd %2, 32\n\t" \
: "=r" (cr), "=r" (th), "=r" (tl) \
: "r" (AH), "r" (AL), "r" (BH), "r" (BL), "i" (PS) \
: "v0", "v1", "v2");
#ifdef __has_builtin
#if !__has_builtin(__builtin_bcdsub)
#define NO_BUILTIN_BCDSUB
#endif
#endif
#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
do { \
int cr = 0; \
uint64_t th, tl; \
BCDSUB(AH, AL, BH, BL, PS); \
if (TH != UNDEF || TL != UNDEF) { \
assert(tl == TL); \
assert(th == TH); \
} \
assert((cr >> 4) == CR6); \
#ifdef NO_BUILTIN_BCDSUB
#define BCDSUB(T, A, B, PS) \
".long 4 << 26 | (" #T ") << 21 | (" #A ") << 16 | (" #B ") << 11" \
" | 1 << 10 | (" #PS ") << 9 | 65\n\t"
#else
#define BCDSUB(T, A, B, PS) "bcdsub. " #T ", " #A ", " #B ", " #PS "\n\t"
#endif
#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
do { \
int cr = 0; \
uint64_t th, tl; \
/* \
* Use GPR pairs to load the VSR values and place the resulting VSR and\
* CR6 in th, tl, and cr. Note that we avoid newer instructions (e.g., \
* mtvsrdd/mfvsrld) so we can run this test on POWER8 machines. \
*/ \
asm ("mtvsrd 32, %3\n\t" \
"mtvsrd 33, %4\n\t" \
"xxmrghd 32, 32, 33\n\t" \
"mtvsrd 33, %5\n\t" \
"mtvsrd 34, %6\n\t" \
"xxmrghd 33, 33, 34\n\t" \
BCDSUB(0, 0, 1, PS) \
"mfocrf %0, 0b10\n\t" \
"mfvsrd %1, 32\n\t" \
"xxswapd 32, 32\n\t" \
"mfvsrd %2, 32\n\t" \
: "=r" (cr), "=r" (th), "=r" (tl) \
: "r" (AH), "r" (AL), "r" (BH), "r" (BL) \
: "v0", "v1", "v2"); \
if (TH != UNDEF || TL != UNDEF) { \
assert(tl == TL); \
assert(th == TH); \
} \
assert((cr >> 4) == CR6); \
} while (0)
/*