PowerPC prep/chrp/pmac support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@865 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
2444ca413b
commit
642012017c
@ -244,8 +244,8 @@ ifeq ($(TARGET_ARCH), ppc)
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VL_OBJS+= ppc.o
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# PREP hardware support
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VL_OBJS+= ide.o ne2000.o pckbd.o vga.o sb16.o dma.o oss.o
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VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o ppc_prep.o
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#VL_OBJS+= hw.o of.o setup.o
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VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o
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VL_OBJS+= ppc_prep.o ppc_chrp.o
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endif
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ifdef CONFIG_GDBSTUB
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VL_OBJS+=gdbstub.o
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248
hw/ppc.c
248
hw/ppc.c
@ -23,11 +23,6 @@
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*/
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#include "vl.h"
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void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename);
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/*****************************************************************************/
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/* PPC time base and decrementer emulation */
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//#define DEBUG_TB
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@ -202,14 +197,249 @@ void cpu_ppc_reset (CPUState *env)
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}
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#endif
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static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
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{
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cpu_outb(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readb (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr & 0xffff);
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return ret;
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}
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static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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cpu_outw(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readw (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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return ret;
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}
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static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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cpu_outl(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readl (target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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return ret;
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}
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CPUWriteMemoryFunc *PPC_io_write[] = {
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&PPC_io_writeb,
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&PPC_io_writew,
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&PPC_io_writel,
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};
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CPUReadMemoryFunc *PPC_io_read[] = {
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&PPC_io_readb,
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&PPC_io_readw,
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&PPC_io_readl,
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};
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/*****************************************************************************/
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/* Debug port */
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val)
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{
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addr &= 0xF;
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switch (addr) {
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case 0:
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printf("%c", val);
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break;
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case 1:
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printf("\n");
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fflush(stdout);
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break;
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case 2:
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printf("Set loglevel to %04x\n", val);
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cpu_set_log(val);
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break;
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}
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}
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/*****************************************************************************/
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/* NVRAM helpers */
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void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value);
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}
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uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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m48t59_set_addr(nvram, addr);
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return m48t59_read(nvram);
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}
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void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 8);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, value & 0xFF);
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}
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uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 24);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, (value >> 16) & 0xFF);
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m48t59_set_addr(nvram, addr + 2);
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m48t59_write(nvram, (value >> 8) & 0xFF);
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m48t59_set_addr(nvram, addr + 3);
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m48t59_write(nvram, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
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{
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uint32_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 24;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram) << 16;
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m48t59_set_addr(nvram, addr + 2);
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tmp |= m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 3);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t59_set_addr(nvram, addr + i);
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m48t59_write(nvram, str[i]);
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}
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m48t59_set_addr(nvram, addr + max - 1);
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m48t59_write(nvram, '\0');
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}
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int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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int i;
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memset(dst, 0, max);
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for (i = 0; i < max; i++) {
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dst[i] = NVRAM_get_byte(nvram, addr + i);
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if (dst[i] == '\0')
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break;
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}
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return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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const unsigned char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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uint32_t cmdline, uint32_t cmdline_size,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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NVRAM_set_lword(nvram, 0x40, cmdline);
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NVRAM_set_lword(nvram, 0x44, cmdline_size);
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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crc = NVRAM_compute_crc(nvram, 0x00, 0x5C);
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NVRAM_set_word(nvram, 0x5C, crc);
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return 0;
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}
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/*****************************************************************************/
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void ppc_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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/* For now, only PREP is supported */
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return ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
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snapshot, kernel_filename, kernel_cmdline,
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initrd_filename);
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if (prep_enabled) {
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ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
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snapshot, kernel_filename, kernel_cmdline,
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initrd_filename);
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} else {
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ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
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snapshot, kernel_filename, kernel_cmdline,
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initrd_filename);
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}
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}
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107
hw/ppc_chrp.c
Normal file
107
hw/ppc_chrp.c
Normal file
@ -0,0 +1,107 @@
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/*
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* QEMU PPC CHRP/PMAC hardware System Emulator
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#define BIOS_FILENAME "ppc_rom.bin"
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#define NVRAM_SIZE 0x2000
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/* PowerPC PREP hardware initialisation */
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void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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m48t59_t *nvram;
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int PPC_io_memory;
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int ret, linux_boot, i, fd;
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unsigned long bios_offset;
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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ret = load_image(buf, phys_ram_base + bios_offset);
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if (ret != BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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exit(1);
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}
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cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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cpu_single_env->nip = 0xfffffffc;
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/* Register CPU as a 74x/75x */
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cpu_ppc_register(cpu_single_env, 0x00080000);
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
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isa_mem_base = 0xc0000000;
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pci_pmac_init();
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/* Register 64 KB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
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cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
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// cpu_register_physical_memory(0xfe000000, 0xfe010000, PPC_io_memory);
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/* init basic PC hardware */
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vga_initialize(ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size, 1);
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// openpic = openpic_init(0x00000000, 0xF0000000, 1);
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// pic_init(openpic);
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pic_init();
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// pit = pit_init(0x40, 0);
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/* XXX: use Mac Serial port */
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fd = serial_open_device();
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serial_init(0x3f8, 4, fd);
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(&nd_table[i]);
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}
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pci_ide_init(bs_table);
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kbd_init();
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nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
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PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
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0, 0,
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0,
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0,
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0, 0,
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/* XXX: need an option to load a NVRAM image */
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0
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);
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/* Special port to get debug messages from Open-Firmware */
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register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
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register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);
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pci_ppc_bios_init();
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}
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1062
hw/ppc_prep.c
1062
hw/ppc_prep.c
File diff suppressed because it is too large
Load Diff
27
vl.h
27
vl.h
@ -594,15 +594,34 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename);
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ppc_tb_t *cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
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struct sysctrl_t;
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int prep_NVRAM_init (struct sysctrl_t *sysctrl, uint32_t RAM_size,
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uint32_t BIOS_size, int boot_device,
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uint32_t kernel_image);
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
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extern CPUWriteMemoryFunc *PPC_io_write[];
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extern CPUReadMemoryFunc *PPC_io_read[];
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extern int prep_enabled;
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/* NVRAM helpers */
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#include "hw/m48t59.h"
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void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
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uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
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void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
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uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
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void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
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uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
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void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max);
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int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
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void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
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uint32_t start, uint32_t count);
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int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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const unsigned char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
|
||||
uint32_t cmdline, uint32_t cmdline_size,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image);
|
||||
|
||||
/* monitor.c */
|
||||
void monitor_init(void);
|
||||
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user