target/arm: Implement the STGP instruction
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
c15294c1e3
commit
6439d67fc9
|
@ -2690,7 +2690,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
|
||||||
* +-----+-------+---+---+-------+---+-------+-------+------+------+
|
* +-----+-------+---+---+-------+---+-------+-------+------+------+
|
||||||
*
|
*
|
||||||
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
|
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
|
||||||
* LDPSW 01
|
* LDPSW/STGP 01
|
||||||
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
|
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
|
||||||
* V: 0 -> GPR, 1 -> Vector
|
* V: 0 -> GPR, 1 -> Vector
|
||||||
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
|
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
|
||||||
|
@ -2715,6 +2715,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
|
||||||
bool is_signed = false;
|
bool is_signed = false;
|
||||||
bool postindex = false;
|
bool postindex = false;
|
||||||
bool wback = false;
|
bool wback = false;
|
||||||
|
bool set_tag = false;
|
||||||
|
|
||||||
TCGv_i64 clean_addr, dirty_addr;
|
TCGv_i64 clean_addr, dirty_addr;
|
||||||
|
|
||||||
|
@ -2727,6 +2728,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
|
||||||
|
|
||||||
if (is_vector) {
|
if (is_vector) {
|
||||||
size = 2 + opc;
|
size = 2 + opc;
|
||||||
|
} else if (opc == 1 && !is_load) {
|
||||||
|
/* STGP */
|
||||||
|
if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
|
||||||
|
unallocated_encoding(s);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
size = 3;
|
||||||
|
set_tag = true;
|
||||||
} else {
|
} else {
|
||||||
size = 2 + extract32(opc, 1, 1);
|
size = 2 + extract32(opc, 1, 1);
|
||||||
is_signed = extract32(opc, 0, 1);
|
is_signed = extract32(opc, 0, 1);
|
||||||
|
@ -2767,7 +2776,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
offset <<= size;
|
offset <<= (set_tag ? LOG2_TAG_GRANULE : size);
|
||||||
|
|
||||||
if (rn == 31) {
|
if (rn == 31) {
|
||||||
gen_check_sp_alignment(s);
|
gen_check_sp_alignment(s);
|
||||||
|
@ -2777,8 +2786,22 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
|
||||||
if (!postindex) {
|
if (!postindex) {
|
||||||
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
|
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
|
||||||
}
|
}
|
||||||
clean_addr = clean_data_tbi(s, dirty_addr);
|
|
||||||
|
|
||||||
|
if (set_tag) {
|
||||||
|
if (!s->ata) {
|
||||||
|
/*
|
||||||
|
* TODO: We could rely on the stores below, at least for
|
||||||
|
* system mode, if we arrange to add MO_ALIGN_16.
|
||||||
|
*/
|
||||||
|
gen_helper_stg_stub(cpu_env, dirty_addr);
|
||||||
|
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
|
||||||
|
gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
|
||||||
|
} else {
|
||||||
|
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
clean_addr = clean_data_tbi(s, dirty_addr);
|
||||||
if (is_vector) {
|
if (is_vector) {
|
||||||
if (is_load) {
|
if (is_load) {
|
||||||
do_fp_ld(s, rt, clean_addr, size);
|
do_fp_ld(s, rt, clean_addr, size);
|
||||||
|
|
Loading…
Reference in New Issue