target-arm: Move TB flags down to fill gap
Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env)
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/* We store the bottom two bits of the CPAR as TB flags and handle
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* checks on the other bits at runtime
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*/
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#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
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#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
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#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
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/* Indicates whether cp register reads and writes by guest code should access
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* the secure or nonsecure bank of banked registers; note that this is not
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* the same thing as the current security state of the processor!
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*/
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#define ARM_TBFLAG_NS_SHIFT 22
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#define ARM_TBFLAG_NS_SHIFT 19
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#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
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/* Bit usage when in AArch64 state: currently we have no A64 specific bits */
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