libqos/ahci: add ahci command functions
This patch adds the AHCICommand structure, and a set of functions to
operate on the structure.
ahci_command_create - Initialize and create a new AHCICommand in memory
ahci_command_free - Destroy this object.
ahci_command_set_buffer - Set where the guest memory DMA buffer is.
ahci_command_commit - Write this command to the AHCI HBA.
ahci_command_issue - Issue the committed command synchronously.
ahci_command_issue_async - Issue the committed command asynchronously.
ahci_command_wait - Wait for an asynchronous command to finish.
ahci_command_slot - Get the number of the command slot we committed to.
Helpers:
size_to_prdtl - Calculate the required minimum PRDTL size from
a buffer size.
ahci_command_find - Given an ATA command mnemonic, look it up in the
properties table to obtain info about the command.
command_header_init - Initialize the command header with sane values.
command_table_init - Initialize the command table with sane values.
[Peter Maydell <peter.maydell@linaro.org> reported the following clang
warning:
tests/libqos/ahci.c:598:3: warning: redefinition
of typedef 'AHCICommand' is a C11 feature
[-Wtypedef-redefinition]
} AHCICommand;
I have replaced typedef struct ... AHCICommand; with struct ... ;
--Stefan]
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
Message-id: 1423158090-25580-13-git-send-email-jsnow@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
John Snow
Stefan Hajnoczi
parent
716b64079c
commit
64a5a272e3
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@ -657,30 +657,28 @@ static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
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*/
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static void ahci_test_identify(AHCIQState *ahci)
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{
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RegH2DFIS fis;
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AHCICommandHeader cmd;
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PRD prd;
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uint32_t data_ptr;
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uint16_t buff[256];
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unsigned i;
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int rc;
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AHCICommand *cmd;
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uint8_t cx;
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uint64_t table;
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g_assert(ahci != NULL);
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/* We need to:
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* (1) Create a Command Table Buffer and update the Command List Slot #0
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* to point to this buffer.
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* (2) Construct an FIS host-to-device command structure, and write it to
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* (1) Create a data buffer for the IDENTIFY response to be sent to,
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* (2) Create a Command Table Buffer
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* (3) Construct an FIS host-to-device command structure, and write it to
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* the top of the command table buffer.
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* (3) Create a data buffer for the IDENTIFY response to be sent to
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* (4) Create a Physical Region Descriptor that points to the data buffer,
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* and write it to the bottom (offset 0x80) of the command table.
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* (5) Now, PxCLB points to the command list, command 0 points to
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* (5) Obtain a Command List slot, and update this header to point to
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* the Command Table we built above.
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* (6) Now, PxCLB points to the command list, command 0 points to
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* our table, and our table contains an FIS instruction and a
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* PRD that points to our rx buffer.
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* (6) We inform the HBA via PxCI that there is a command ready in slot #0.
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* (7) We inform the HBA via PxCI that there is a command ready in slot #0.
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*/
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/* Pick the first implemented and running port */
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@ -690,61 +688,24 @@ static void ahci_test_identify(AHCIQState *ahci)
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/* Clear out the FIS Receive area and any pending interrupts. */
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ahci_port_clear(ahci, i);
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/* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
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/* We need at least one PRD, so round up to the nearest 0x80 multiple. */
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table = ahci_alloc(ahci, CMD_TBL_SIZ(1));
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g_assert(table);
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ASSERT_BIT_CLEAR(table, 0x7F);
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/* Create a data buffer ... where we will dump the IDENTIFY data to. */
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/* Create a data buffer where we will dump the IDENTIFY data to. */
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data_ptr = ahci_alloc(ahci, 512);
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g_assert(data_ptr);
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/* pick a command slot (should be 0!) */
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cx = ahci_pick_cmd(ahci, i);
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/* Construct our Command Header (set_command_header handles endianness.) */
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memset(&cmd, 0x00, sizeof(cmd));
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cmd.flags = 5; /* reg_h2d_fis is 5 double-words long */
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cmd.flags |= CMDH_CLR_BSY; /* clear PxTFD.STS.BSY when done */
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cmd.prdtl = 1; /* One PRD table entry. */
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cmd.prdbc = 0;
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cmd.ctba = table;
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/* Construct our PRD, noting that DBC is 0-indexed. */
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prd.dba = cpu_to_le64(data_ptr);
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prd.res = 0;
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/* 511+1 bytes, request DPS interrupt */
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prd.dbc = cpu_to_le32(511 | 0x80000000);
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/* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
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memset(&fis, 0x00, sizeof(fis));
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fis.fis_type = REG_H2D_FIS; /* Register Host-to-Device FIS */
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fis.command = CMD_IDENTIFY;
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fis.device = 0;
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fis.flags = REG_H2D_FIS_CMD; /* Indicate this is a command FIS */
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/* We've committed nothing yet, no interrupts should be posted yet. */
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g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
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/* Commit the Command FIS to the Command Table */
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ahci_write_fis(ahci, &fis, table);
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/* Commit the PRD entry to the Command Table */
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memwrite(table + 0x80, &prd, sizeof(prd));
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/* Commit Command #cx, pointing to the Table, to the Command List Buffer. */
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ahci_set_command_header(ahci, i, cx, &cmd);
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/* Construct the Command Table (FIS and PRDT) and Command Header */
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cmd = ahci_command_create(CMD_IDENTIFY);
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ahci_command_set_buffer(cmd, data_ptr);
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/* Write the command header and PRDT to guest memory */
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ahci_command_commit(ahci, cmd, i);
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/* Everything is in place, but we haven't given the go-ahead yet,
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* so we should find that there are no pending interrupts yet. */
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g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
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/* Issue Command #cx via PxCI */
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ahci_px_wreg(ahci, i, AHCI_PX_CI, (1 << cx));
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while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
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usleep(50);
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}
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ahci_command_issue(ahci, cmd);
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cx = ahci_command_slot(cmd);
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/* Check registers for post-command consistency */
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ahci_port_check_error(ahci, i);
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/* BUG: we expect AHCI_PX_IS_DPS to be set. */
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@ -539,3 +539,205 @@ unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
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g_test_message("All command slots were busy.");
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g_assert_not_reached();
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}
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inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
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{
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/* Each PRD can describe up to 4MiB */
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g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
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g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
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return (bytes + bytes_per_prd - 1) / bytes_per_prd;
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}
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struct AHCICommand {
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/* Test Management Data */
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uint8_t name;
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uint8_t port;
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uint8_t slot;
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uint32_t interrupts;
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uint64_t xbytes;
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uint32_t prd_size;
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uint64_t buffer;
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AHCICommandProp *props;
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/* Data to be transferred to the guest */
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AHCICommandHeader header;
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RegH2DFIS fis;
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void *atapi_cmd;
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};
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static AHCICommandProp *ahci_command_find(uint8_t command_name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
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if (ahci_command_properties[i].cmd == command_name) {
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return &ahci_command_properties[i];
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}
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}
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return NULL;
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}
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/**
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* Initializes a basic command header in memory.
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* We assume that this is for an ATA command using RegH2DFIS.
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*/
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static void command_header_init(AHCICommand *cmd)
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{
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AHCICommandHeader *hdr = &cmd->header;
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AHCICommandProp *props = cmd->props;
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hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */
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hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */
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if (props->write) {
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hdr->flags |= CMDH_WRITE;
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}
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if (props->atapi) {
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hdr->flags |= CMDH_ATAPI;
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}
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/* Other flags: PREFETCH, RESET, and BIST */
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hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
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hdr->prdbc = 0;
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hdr->ctba = 0;
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}
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static void command_table_init(AHCICommand *cmd)
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{
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RegH2DFIS *fis = &(cmd->fis);
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fis->fis_type = REG_H2D_FIS;
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fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */
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fis->command = cmd->name;
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cmd->fis.feature_low = 0x00;
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cmd->fis.feature_high = 0x00;
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if (cmd->props->lba28 || cmd->props->lba48) {
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cmd->fis.device = ATA_DEVICE_LBA;
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}
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cmd->fis.count = (cmd->xbytes / AHCI_SECTOR_SIZE);
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cmd->fis.icc = 0x00;
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cmd->fis.control = 0x00;
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memset(cmd->fis.aux, 0x00, ARRAY_SIZE(cmd->fis.aux));
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}
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AHCICommand *ahci_command_create(uint8_t command_name)
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{
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AHCICommandProp *props = ahci_command_find(command_name);
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AHCICommand *cmd;
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g_assert(props);
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cmd = g_malloc0(sizeof(AHCICommand));
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g_assert(!(props->dma && props->pio));
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g_assert(!(props->lba28 && props->lba48));
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g_assert(!(props->read && props->write));
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g_assert(!props->size || props->data);
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/* Defaults and book-keeping */
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cmd->props = props;
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cmd->name = command_name;
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cmd->xbytes = props->size;
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cmd->prd_size = 4096;
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cmd->buffer = 0xabad1dea;
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cmd->interrupts = AHCI_PX_IS_DHRS;
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/* BUG: We expect the DPS interrupt for data commands */
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/* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */
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/* BUG: We expect the DMA Setup interrupt for DMA commands */
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/* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */
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cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0;
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command_header_init(cmd);
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command_table_init(cmd);
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return cmd;
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}
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void ahci_command_free(AHCICommand *cmd)
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{
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g_free(cmd);
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}
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void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
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{
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cmd->buffer = buffer;
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}
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void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
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{
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uint16_t i, prdtl;
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uint64_t table_size, table_ptr, remaining;
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PRD prd;
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/* This command is now tied to this port/command slot */
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cmd->port = port;
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cmd->slot = ahci_pick_cmd(ahci, port);
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/* Create a buffer for the command table */
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prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
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table_size = CMD_TBL_SIZ(prdtl);
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table_ptr = ahci_alloc(ahci, table_size);
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g_assert(table_ptr);
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/* AHCI 1.3: Must be aligned to 0x80 */
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g_assert((table_ptr & 0x7F) == 0x00);
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cmd->header.ctba = table_ptr;
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/* Commit the command header and command FIS */
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ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
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ahci_write_fis(ahci, &(cmd->fis), table_ptr);
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/* Construct and write the PRDs to the command table */
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g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
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remaining = cmd->xbytes;
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for (i = 0; i < prdtl; ++i) {
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prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
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prd.res = 0;
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if (remaining > cmd->prd_size) {
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/* Note that byte count is 0-based. */
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prd.dbc = cpu_to_le32(cmd->prd_size - 1);
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remaining -= cmd->prd_size;
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} else {
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/* Again, dbc is 0-based. */
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prd.dbc = cpu_to_le32(remaining - 1);
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remaining = 0;
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}
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prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
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/* Commit the PRD entry to the Command Table */
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memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
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&prd, sizeof(PRD));
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}
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/* Bookmark the PRDTL and CTBA values */
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ahci->port[port].ctba[cmd->slot] = table_ptr;
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ahci->port[port].prdtl[cmd->slot] = prdtl;
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}
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void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
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{
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if (cmd->props->ncq) {
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ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
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}
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ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
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}
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void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
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{
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/* We can't rely on STS_BSY until the command has started processing.
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* Therefore, we also use the Command Issue bit as indication of
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* a command in-flight. */
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while (BITSET(ahci_px_rreg(ahci, cmd->port, AHCI_PX_TFD),
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AHCI_PX_TFD_STS_BSY) ||
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BITSET(ahci_px_rreg(ahci, cmd->port, AHCI_PX_CI), (1 << cmd->slot))) {
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usleep(50);
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}
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}
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void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
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{
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ahci_command_issue_async(ahci, cmd);
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ahci_command_wait(ahci, cmd);
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}
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uint8_t ahci_command_slot(AHCICommand *cmd)
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{
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return cmd->slot;
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}
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@ -418,6 +418,9 @@ typedef struct PRD {
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uint32_t dbc; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
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} __attribute__((__packed__)) PRD;
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/* Opaque, defined within ahci.c */
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typedef struct AHCICommand AHCICommand;
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/*** Macro Utilities ***/
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#define BITANY(data, mask) (((data) & (mask)) != 0)
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#define BITSET(data, mask) (((data) & (mask)) == (mask))
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@ -517,5 +520,20 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
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void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot);
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void ahci_write_fis(AHCIQState *ahci, RegH2DFIS *fis, uint64_t addr);
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unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port);
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unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd);
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/* Command Lifecycle */
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AHCICommand *ahci_command_create(uint8_t command_name);
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void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port);
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void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd);
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void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd);
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void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd);
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void ahci_command_free(AHCICommand *cmd);
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/* Command adjustments */
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void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer);
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/* Command Misc */
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uint8_t ahci_command_slot(AHCICommand *cmd);
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#endif
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