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OpenRISC FPU Fix for 8.1 

A patch to pass the correct exception address when handling floating
 point exceptions.
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Merge tag 'or1k-pull-request-20230809' of https://github.com/stffrdhrn/qemu into staging

OpenRISC FPU Fix for 8.1

A patch to pass the correct exception address when handling floating
point exceptions.

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* tag 'or1k-pull-request-20230809' of https://github.com/stffrdhrn/qemu:
  target/openrisc: Set EPCR to next PC on FPE exceptions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-08-09 15:05:02 -07:00
parent e53e2e2a1b 765fdc1e83
commit 64d3be986f
1 changed files with 4 additions and 3 deletions
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7
target/openrisc/interrupt.c
View File

@ -34,9 +34,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
int exception = cs->exception_index;
env->epcr = env->pc;
if (exception == EXCP_SYSCALL) {
env->epcr += 4;
}
/* When we have an illegal instruction the error effective address
shall be set to the illegal instruction address. */
if (exception == EXCP_ILLEGAL) {
@ -63,6 +61,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->epcr -= 4;
} else {
env->sr &= ~SR_DSX;
if (exception == EXCP_SYSCALL || exception == EXCP_FPE) {
env->epcr += 4;
}
}
if (exception > 0 && exception < EXCP_NR) {