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Fourth RISC-V PR for 6.1 release

Browse Source 
- Code cleanups
  - Documentation improvements
  - Hypervisor extension improvements with hideleg and hedeleg
  - sifive_u fixes
  - OpenTitan register layout updates
  - Fix coverity issue
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210715' into staging

Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates
 - Fix coverity issue

# gpg: Signature made Thu 15 Jul 2021 08:14:00 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210715:
  hw/riscv/boot: Check the error of fdt_pack()
  hw/riscv: opentitan: Add the flash alias
  hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
  char: ibex_uart: Update the register layout
  hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
  hw/riscv: sifive_u: Correct the CLINT timebase frequency
  docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
  target/riscv: hardwire bits in hideleg and hedeleg
  docs/system: riscv: Add documentation for virt machine
  docs/system: riscv: Fix CLINT name in the sifive_u doc
  target/riscv: csr: Remove redundant check in fp csr read/write routines
  target/riscv: pmp: Fix some typos

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-07-16 09:03:11 +01:00
commit 65388f4044
11 changed files with 257 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
docs/system/riscv/microchip-icicle-kit.rst
View File

@ -47,13 +47,13 @@ The user provided DTB should have the following requirements:
QEMU follows below truth table to select which payload to execute:
===== ========== =======
-bios -kernel payload
===== ========== =======
N N HSS
Y don't care HSS
N Y kernel
===== ========== =======
===== ========== ========== =======
-bios -kernel -dtb payload
===== ========== ========== =======
N N don't care HSS
Y don't care don't care HSS
N Y Y kernel
===== ========== ========== =======
The memory is set to 1537 MiB by default which is the minimum required high
memory size by HSS. A sanity check on ram size is performed in the machine
@ -106,4 +106,44 @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the
second serial port. U-Boot will automatically load the Linux kernel from
the SD card image.
Direct Kernel Boot
------------------
Sometimes we just want to test booting a new kernel, and transforming the
kernel image to the format required by the HSS bootflow is tedious. We can
use '-kernel' for direct kernel booting just like other RISC-V machines do.
In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
used to boot an S-mode payload like U-Boot or OS kernel directly.
For example, the following commands show building a U-Boot image from U-Boot
mainline v2021.07 for the Microchip Icicle Kit board:
.. code-block:: bash
$ export CROSS_COMPILE=riscv64-linux-
$ make microchip_mpfs_icicle_defconfig
Then we can boot the machine by:
.. code-block:: bash
$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \
-sd path/to/sdcard.img \
-nic user,model=cadence_gem \
-nic tap,ifname=tap,model=cadence_gem,script=no \
-display none -serial stdio \
-kernel path/to/u-boot/build/dir/u-boot.bin \
-dtb path/to/u-boot/build/dir/u-boot.dtb
CAVEATS:
* Check the "stdout-path" property in the /chosen node in the DTB to determine
which serial port is used for the serial console, e.g.: if the console is set
to the second serial port, change to use "-serial null -serial stdio".
* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image
``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence
``u-boot.bin`` has to be used which does contain one. To use the ELF image,
we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
.. _HSS: https://github.com/polarfire-soc/hart-software-services

2
docs/system/riscv/sifive_u.rst
View File

@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices:
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
* Core Level Interruptor (CLINT)
* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)

138
docs/system/riscv/virt.rst Normal file
View File

@ -0,0 +1,138 @@
'virt' Generic Virtual Platform (``virt``)
==========================================
The `virt` board is a platform which does not correspond to any real hardware;
it is designed for use in virtual machines. It is the recommended board type
if you simply want to run a guest such as Linux and do not care about
reproducing the idiosyncrasies and limitations of a particular bit of
real-world hardware.
Supported devices
-----------------
The ``virt`` machine supports the following devices:
* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* CFI parallel NOR flash memory
* 1 NS16550 compatible UART
* 1 Google Goldfish RTC
* 1 SiFive Test device
* 8 virtio-mmio transport devices
* 1 generic PCIe host bridge
* The fw_cfg device that allows a guest to obtain data from QEMU
Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
enables the hypervisor extension for RV64.
Hardware configuration information
----------------------------------
The ``virt`` machine automatically generates a device tree blob ("dtb")
which it passes to the guest, if there is no ``-dtb`` option. This provides
information about the addresses, interrupt lines and other configuration of
the various devices in the system. Guest software should discover the devices
that are present in the generated DTB.
If users want to provide their own DTB, they can use the ``-dtb`` option.
These DTBs should have the following requirements:
* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
* The /memory reg size should match QEMU’s selected ram_size via ``-m``
* Should contain a node for the CLINT device with a compatible string
"riscv,clint0" if using with OpenSBI BIOS images
Boot options
------------
The ``virt`` machine can start using the standard -kernel functionality
for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader
with the default OpenSBI firmware image as the -bios. It also supports
the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
firmware and U-Boot proper (S-mode), using the standard -bios functionality.
Running Linux kernel
--------------------
Linux mainline v5.12 release is tested at the time of writing. To build a
Linux mainline kernel that can be booted by the ``virt`` machine in
64-bit mode, simply configure the kernel using the defconfig configuration:
.. code-block:: bash
$ export ARCH=riscv
$ export CROSS_COMPILE=riscv64-linux-
$ make defconfig
$ make
To boot the newly built Linux kernel in QEMU with the ``virt`` machine:
.. code-block:: bash
$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
-display none -serial stdio \
-kernel arch/riscv/boot/Image \
-initrd /path/to/rootfs.cpio \
-append "root=/dev/ram"
To build a Linux mainline kernel that can be booted by the ``virt`` machine
in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
fix the 32-bit boot issue for Linux kernel v5.12.
.. code-block:: bash
$ export ARCH=riscv
$ export CROSS_COMPILE=riscv64-linux-
$ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch
$ git am riscv.patch
$ make rv32_defconfig
$ make
Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command
line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit
applications shall be used in order for kernel to boot to user space.
Running U-Boot
--------------
U-Boot mainline v2021.04 release is tested at the time of writing. To build an
S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use
the qemu-riscv64_smode_defconfig with similar commands as described above for Linux:
.. code-block:: bash
$ export CROSS_COMPILE=riscv64-linux-
$ make qemu-riscv64_smode_defconfig
Boot the 64-bit U-Boot S-mode image directly:
.. code-block:: bash
$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
-display none -serial stdio \
-kernel /path/to/u-boot.bin
To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image
that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together,
build the U-Boot images using riscv64_spl_defconfig:
.. code-block:: bash
$ export CROSS_COMPILE=riscv64-linux-
$ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
$ make qemu-riscv64_spl_defconfig
The minimal QEMU commands to run U-Boot SPL are:
.. code-block:: bash
$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
-display none -serial stdio \
-bios /path/to/u-boot-spl \
-device loader,file=/path/to/u-boot.itb,addr=0x80200000
To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.

1
docs/system/target-riscv.rst
View File

@ -69,6 +69,7 @@ undocumented; you can get a complete list by running
riscv/microchip-icicle-kit
riscv/shakti-c
riscv/sifive_u
riscv/virt
RISC-V CPU firmware
-------------------

19
hw/char/ibex_uart.c
View File

@ -42,7 +42,8 @@ REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
REG32(CTRL, 0x0C)
REG32(ALERT_TEST, 0x0C)
REG32(CTRL, 0x10)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
@ -52,25 +53,25 @@ REG32(CTRL, 0x0C)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
REG32(STATUS, 0x10)
REG32(STATUS, 0x14)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
REG32(RDATA, 0x14)
REG32(WDATA, 0x18)
REG32(FIFO_CTRL, 0x1c)
REG32(RDATA, 0x18)
REG32(WDATA, 0x1C)
REG32(FIFO_CTRL, 0x20)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
REG32(FIFO_STATUS, 0x20)
REG32(FIFO_STATUS, 0x24)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
REG32(OVRD, 0x24)
REG32(VAL, 0x28)
REG32(TIMEOUT_CTRL, 0x2c)
REG32(OVRD, 0x28)
REG32(VAL, 0x2C)
REG32(TIMEOUT_CTRL, 0x30)
static void ibex_uart_update_irqs(IbexUartState *s)
{

6
hw/riscv/boot.c
View File

@ -182,7 +182,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
{
uint32_t temp, fdt_addr;
hwaddr dram_end = dram_base + mem_size;
int fdtsize = fdt_totalsize(fdt);
int ret, fdtsize = fdt_totalsize(fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
@ -198,7 +198,9 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
temp = MIN(dram_end, 3072 * MiB);
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
fdt_pack(fdt);
ret = fdt_pack(fdt);
/* Should only fail if we've built a corrupted tree */
g_assert(ret == 0);
/* copy in the device tree */
qemu_fdt_dumpdtb(fdt, fdtsize);

9
hw/riscv/opentitan.c
View File

@ -58,6 +58,8 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
static void opentitan_board_init(MachineState *machine)
@ -133,8 +135,13 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
/* Flash memory */
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
memmap[IBEX_DEV_FLASH].size, &error_fatal);
memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
"riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
memmap[IBEX_DEV_FLASH_VIRTUAL].size);
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
&s->flash_mem);
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
&s->flash_alias);
/* PLIC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
@ -217,6 +224,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
create_unimplemented_device("riscv.lowrisc.ibex.peri",
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
}
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

12
hw/riscv/sifive_u.c
View File

@ -62,6 +62,9 @@
#include <libfdt.h>
/* CLINT timebase frequency */
#define CLINT_TIMEBASE_FREQ 1000000
static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
SIFIVE_CLINT_TIMEBASE_FREQ);
CLINT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
@ -599,10 +602,10 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* reset vector */
uint32_t reset_vec[11] = {
uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
0,
0,
@ -610,6 +613,7 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr, /* start: .dword */
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
0x00000000,
/* fw_dyn: */
};
@ -847,7 +851,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;

3
include/hw/riscv/opentitan.h
View File

@ -40,6 +40,7 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_mem;
MemoryRegion rom;
MemoryRegion flash_alias;
};
typedef struct OpenTitanState {
@ -54,6 +55,7 @@ enum {
IBEX_DEV_ROM,
IBEX_DEV_RAM,
IBEX_DEV_FLASH,
IBEX_DEV_FLASH_VIRTUAL,
IBEX_DEV_UART,
IBEX_DEV_GPIO,
IBEX_DEV_SPI,
@ -81,6 +83,7 @@ enum {
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_OTBN,
IBEX_DEV_PERI,
};
enum {

78
target/riscv/csr.c
View File

@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env);
return RISCV_EXCP_NONE;
}
@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
static RISCVException read_frm(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm;
return RISCV_EXCP_NONE;
}
@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
static RISCVException read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
if (vs(env, csrno) >= 0) {
@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
@ -435,28 +411,36 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
(1ULL << (RISCV_EXCP_BREAKPOINT)) |
(1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
(1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
(1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_U_ECALL)) |
(1ULL << (RISCV_EXCP_S_ECALL)) |
(1ULL << (RISCV_EXCP_VS_ECALL)) |
(1ULL << (RISCV_EXCP_M_ECALL)) |
(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
(1ULL << (RISCV_EXCP_BREAKPOINT)) | \
(1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_U_ECALL)) | \
(1ULL << (RISCV_EXCP_S_ECALL)) | \
(1ULL << (RISCV_EXCP_VS_ECALL)) | \
(1ULL << (RISCV_EXCP_M_ECALL)) | \
(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
~((1ULL << (RISCV_EXCP_S_ECALL)) |
(1ULL << (RISCV_EXCP_VS_ECALL)) |
(1ULL << (RISCV_EXCP_M_ECALL)) |
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR;
@ -644,7 +628,7 @@ static RISCVException read_medeleg(CPURISCVState *env, int csrno,
static RISCVException write_medeleg(CPURISCVState *env, int csrno,
target_ulong val)
{
env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
return RISCV_EXCP_NONE;
}
@ -1063,7 +1047,7 @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
target_ulong val)
{
env->hedeleg = val;
env->hedeleg = val & vs_delegable_excps;
return RISCV_EXCP_NONE;
}
@ -1077,7 +1061,7 @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno,
static RISCVException write_hideleg(CPURISCVState *env, int csrno,
target_ulong val)
{
env->hideleg = val;
env->hideleg = val & vs_delegable_ints;
return RISCV_EXCP_NONE;
}

10
target/riscv/pmp.c
View File

@ -456,7 +456,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
}
/*
* Handle a write to a pmpcfg CSP
* Handle a write to a pmpcfg CSR
*/
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val)
@ -483,7 +483,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
/*
* Handle a read from a pmpcfg CSP
* Handle a read from a pmpcfg CSR
*/
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
@ -502,7 +502,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
/*
* Handle a write to a pmpaddr CSP
* Handle a write to a pmpaddr CSR
*/
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val)
@ -540,7 +540,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
/*
* Handle a read from a pmpaddr CSP
* Handle a read from a pmpaddr CSR
*/
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
{
@ -593,7 +593,7 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
/*
* Calculate the TLB size if the start address or the end address of
* PMP entry is presented in thie TLB page.
* PMP entry is presented in the TLB page.
*/
static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea)