OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

Avoid some brconds

Browse Source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4318 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-05-04 08:06:33 +00:00
parent b5fc09ae52
commit 653ccb8099
1 changed files with 12 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
target-sparc/translate.c
View File

@ -379,9 +379,6 @@ static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
@ -389,18 +386,15 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
}
#ifdef TARGET_SPARC64
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
@ -408,9 +402,9 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
gen_set_label(l1);
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
}
#endif
@ -570,36 +564,30 @@ static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
}
#ifdef TARGET_SPARC64
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
gen_set_label(l1);
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
}
#endif