From 6542aa2eb1804d0995d8461ca55f522f74368940 Mon Sep 17 00:00:00 2001 From: Taylor Simpson Date: Sun, 7 Feb 2021 23:46:17 -0600 Subject: [PATCH] Hexagon (target/hexagon) TCG for instructions with multiple definitions Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_. Signed-off-by: Taylor Simpson Message-Id: <1612763186-18161-28-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson --- target/hexagon/gen_tcg.h | 198 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 target/hexagon/gen_tcg.h diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h new file mode 100644 index 0000000000..a8d9321b42 --- /dev/null +++ b/target/hexagon/gen_tcg.h @@ -0,0 +1,198 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_GEN_TCG_H +#define HEXAGON_GEN_TCG_H + +/* + * Here is a primer to understand the tag names for load/store instructions + * + * Data types + * b signed byte r0 = memb(r2+#0) + * ub unsigned byte r0 = memub(r2+#0) + * h signed half word (16 bits) r0 = memh(r2+#0) + * uh unsigned half word r0 = memuh(r2+#0) + * i integer (32 bits) r0 = memw(r2+#0) + * d double word (64 bits) r1:0 = memd(r2+#0) + * + * Addressing modes + * _io indirect with offset r0 = memw(r1+#4) + * _ur absolute with register offset r0 = memw(r1<<#4+##variable) + * _rr indirect with register offset r0 = memw(r1+r4<<#2) + * gp global pointer relative r0 = memw(gp+#200) + * _sp stack pointer relative r0 = memw(r29+#12) + * _ap absolute set r0 = memw(r1=##variable) + * _pr post increment register r0 = memw(r1++m1) + * _pi post increment immediate r0 = memb(r1++#1) + */ + +/* Macros for complex addressing modes */ +#define GET_EA_ap \ + do { \ + fEA_IMM(UiV); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) +#define GET_EA_pr \ + do { \ + fEA_REG(RxV); \ + fPM_M(RxV, MuV); \ + } while (0) +#define GET_EA_pi \ + do { \ + fEA_REG(RxV); \ + fPM_I(RxV, siV); \ + } while (0) + + +/* Instructions with multiple definitions */ +#define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ + do { \ + fMUST_IMMEXT(UiV); \ + fEA_IMM(UiV); \ + fLOAD(1, SIZE, SIGN, EA, RES); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) + +#define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 1, u) +#define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 1, s) +#define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 2, u) +#define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 2, s) +#define fGEN_TCG_L4_loadri_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RdV, 4, u) +#define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ + fGEN_TCG_LOAD_AP(RddV, 8, u) + +#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE; +#define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE; +#define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE + +/* + * Predicated loads + * Here is a primer to understand the tag names + * + * Predicate used + * t true "old" value if (p0) r0 = memb(r2+#0) + * f false "old" value if (!p0) r0 = memb(r2+#0) + * tnew true "new" value if (p0.new) r0 = memb(r2+#0) + * fnew false "new" value if (!p0.new) r0 = memb(r2+#0) + */ +#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ + do { \ + TCGv LSB = tcg_temp_local_new(); \ + TCGLabel *label = gen_new_label(); \ + GET_EA; \ + PRED; \ + PRED_LOAD_CANCEL(LSB, EA); \ + tcg_gen_movi_tl(RdV, 0); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ + fLOAD(1, SIZE, SIGN, EA, RdV); \ + gen_set_label(label); \ + tcg_temp_free(LSB); \ + } while (0) + +#define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u) +#define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u) +#define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u) +#define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u) +#define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s) +#define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s) +#define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s) +#define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \ + fLSBNEWNOT(PtN), 1, s) + +#define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u) +#define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u) +#define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u) +#define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u) +#define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s) +#define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s) +#define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s) +#define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s) + +#define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u) +#define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u) +#define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u) +#define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u) + +/* Predicated loads into a register pair */ +#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ + do { \ + TCGv LSB = tcg_temp_local_new(); \ + TCGLabel *label = gen_new_label(); \ + GET_EA; \ + PRED; \ + PRED_LOAD_CANCEL(LSB, EA); \ + tcg_gen_movi_i64(RddV, 0); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ + fLOAD(1, 8, u, EA, RddV); \ + gen_set_label(label); \ + tcg_temp_free(LSB); \ + } while (0) + +#define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV)) +#define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV)) +#define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN)) +#define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \ + fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN)) + +/* load-locked and store-locked */ +#define fGEN_TCG_L2_loadw_locked(SHORTCODE) \ + SHORTCODE +#define fGEN_TCG_L4_loadd_locked(SHORTCODE) \ + SHORTCODE +#define fGEN_TCG_S2_storew_locked(SHORTCODE) \ + do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) +#define fGEN_TCG_S4_stored_locked(SHORTCODE) \ + do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) + +#endif