OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

ppc patch queue for 2023-02-05:

Browse Source 
This queue includes patches that aren't PPC specific but benefit/impact
 PPC machines, such as the changes to guestperf.py, mv64361 and sm501. As
 for PPC specific changes we have e500 and PNV_PHB5 fixes.
 -----BEGIN PGP SIGNATURE-----
 
 iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCY99+yRYcZGFuaWVsaGI0
 MTNAZ21haWwuY29tAAoJEDzZypbeAzFkOQsA/1UxMHen/3tW908shrRMwS7WSzDa
 4x0tU4L+bMpEfgVJAQDeKIyIbdajtv4v2XfZyQ9flfUo64cY0xze+T+SDW+fBw==
 =eB7g
 -----END PGP SIGNATURE-----

Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-02-05:

This queue includes patches that aren't PPC specific but benefit/impact
PPC machines, such as the changes to guestperf.py, mv64361 and sm501. As
for PPC specific changes we have e500 and PNV_PHB5 fixes.

# -----BEGIN PGP SIGNATURE-----
#
# iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCY99+yRYcZGFuaWVsaGI0
# MTNAZ21haWwuY29tAAoJEDzZypbeAzFkOQsA/1UxMHen/3tW908shrRMwS7WSzDa
# 4x0tU4L+bMpEfgVJAQDeKIyIbdajtv4v2XfZyQ9flfUo64cY0xze+T+SDW+fBw==
# =eB7g
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 05 Feb 2023 10:02:49 GMT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu:
  hw/display/sm501: Code style fix
  hw/display/sm501: Remove unneeded casts from void pointer
  hw/display/sm501: Remove parenthesis around constant macro definitions
  hw/ppc/pegasos2: Fix a typo in a comment
  ppc/pnv/pci: Fix PHB xscom registers memory region name
  ppc/pnv/pci: Update PHB5 version register
  ppc/pnv/pci: Remove duplicate definition of PNV_PHB5_DEVICE_ID
  ppc/pnv/pci: Cleanup PnvPHBPecState structure
  hw/ppc/e500.c: Attach eSDHC unimplemented region to ccsr_addr_space
  hw/ppc/e500.c: Avoid hardcoding parent device in create_devtree_etsec()
  hw/ppc/e500{, plat}: Drop redundant checks for presence of platform bus
  hw/ppc: Set machine->fdt in e500 machines
  hw/pci-host/mv64361: Reuse pci_swizzle_map_irq_fn
  ppc/pegasos2: Improve readability of VIA south bridge creation
  tests/migration: add support for ppc64le for guestperf.py
  tests/migration: add sysprof-capture-4 as dependency for stress binary

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-02-05 16:49:09 +00:00
commit 6661b8c7fe
9 changed files with 264 additions and 242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

411
hw/display/sm501.c
View File

@ -50,10 +50,10 @@
/* System Configuration area */
/* System config base */
#define SM501_SYS_CONFIG (0x000000)
#define SM501_SYS_CONFIG 0x000000
/* config 1 */
#define SM501_SYSTEM_CONTROL (0x000000)
#define SM501_SYSTEM_CONTROL 0x000000
#define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
#define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
@ -72,13 +72,13 @@
/* miscellaneous control */
#define SM501_MISC_CONTROL (0x000004)
#define SM501_MISC_CONTROL 0x000004
#define SM501_MISC_BUS_SH (0x0)
#define SM501_MISC_BUS_PCI (0x1)
#define SM501_MISC_BUS_XSCALE (0x2)
#define SM501_MISC_BUS_NEC (0x6)
#define SM501_MISC_BUS_MASK (0x7)
#define SM501_MISC_BUS_SH 0x0
#define SM501_MISC_BUS_PCI 0x1
#define SM501_MISC_BUS_XSCALE 0x2
#define SM501_MISC_BUS_NEC 0x6
#define SM501_MISC_BUS_MASK 0x7
#define SM501_MISC_VR_62MB (1 << 3)
#define SM501_MISC_CDR_RESET (1 << 7)
@ -103,22 +103,22 @@
#define SM501_GPIO31_0_CONTROL (0x000008)
#define SM501_GPIO63_32_CONTROL (0x00000C)
#define SM501_DRAM_CONTROL (0x000010)
#define SM501_GPIO31_0_CONTROL 0x000008
#define SM501_GPIO63_32_CONTROL 0x00000C
#define SM501_DRAM_CONTROL 0x000010
/* command list */
#define SM501_ARBTRTN_CONTROL (0x000014)
#define SM501_ARBTRTN_CONTROL 0x000014
/* command list */
#define SM501_COMMAND_LIST_STATUS (0x000024)
#define SM501_COMMAND_LIST_STATUS 0x000024
/* interrupt debug */
#define SM501_RAW_IRQ_STATUS (0x000028)
#define SM501_RAW_IRQ_CLEAR (0x000028)
#define SM501_IRQ_STATUS (0x00002C)
#define SM501_IRQ_MASK (0x000030)
#define SM501_DEBUG_CONTROL (0x000034)
#define SM501_RAW_IRQ_STATUS 0x000028
#define SM501_RAW_IRQ_CLEAR 0x000028
#define SM501_IRQ_STATUS 0x00002C
#define SM501_IRQ_MASK 0x000030
#define SM501_DEBUG_CONTROL 0x000034
/* power management */
#define SM501_POWERMODE_P2X_SRC (1 << 29)
@ -126,74 +126,74 @@
#define SM501_POWERMODE_M_SRC (1 << 12)
#define SM501_POWERMODE_M1_SRC (1 << 4)
#define SM501_CURRENT_GATE (0x000038)
#define SM501_CURRENT_CLOCK (0x00003C)
#define SM501_POWER_MODE_0_GATE (0x000040)
#define SM501_POWER_MODE_0_CLOCK (0x000044)
#define SM501_POWER_MODE_1_GATE (0x000048)
#define SM501_POWER_MODE_1_CLOCK (0x00004C)
#define SM501_SLEEP_MODE_GATE (0x000050)
#define SM501_POWER_MODE_CONTROL (0x000054)
#define SM501_CURRENT_GATE 0x000038
#define SM501_CURRENT_CLOCK 0x00003C
#define SM501_POWER_MODE_0_GATE 0x000040
#define SM501_POWER_MODE_0_CLOCK 0x000044
#define SM501_POWER_MODE_1_GATE 0x000048
#define SM501_POWER_MODE_1_CLOCK 0x00004C
#define SM501_SLEEP_MODE_GATE 0x000050
#define SM501_POWER_MODE_CONTROL 0x000054
/* power gates for units within the 501 */
#define SM501_GATE_HOST (0)
#define SM501_GATE_MEMORY (1)
#define SM501_GATE_DISPLAY (2)
#define SM501_GATE_2D_ENGINE (3)
#define SM501_GATE_CSC (4)
#define SM501_GATE_ZVPORT (5)
#define SM501_GATE_GPIO (6)
#define SM501_GATE_UART0 (7)
#define SM501_GATE_UART1 (8)
#define SM501_GATE_SSP (10)
#define SM501_GATE_USB_HOST (11)
#define SM501_GATE_USB_GADGET (12)
#define SM501_GATE_UCONTROLLER (17)
#define SM501_GATE_AC97 (18)
#define SM501_GATE_HOST 0
#define SM501_GATE_MEMORY 1
#define SM501_GATE_DISPLAY 2
#define SM501_GATE_2D_ENGINE 3
#define SM501_GATE_CSC 4
#define SM501_GATE_ZVPORT 5
#define SM501_GATE_GPIO 6
#define SM501_GATE_UART0 7
#define SM501_GATE_UART1 8
#define SM501_GATE_SSP 10
#define SM501_GATE_USB_HOST 11
#define SM501_GATE_USB_GADGET 12
#define SM501_GATE_UCONTROLLER 17
#define SM501_GATE_AC97 18
/* panel clock */
#define SM501_CLOCK_P2XCLK (24)
#define SM501_CLOCK_P2XCLK 24
/* crt clock */
#define SM501_CLOCK_V2XCLK (16)
#define SM501_CLOCK_V2XCLK 16
/* main clock */
#define SM501_CLOCK_MCLK (8)
#define SM501_CLOCK_MCLK 8
/* SDRAM controller clock */
#define SM501_CLOCK_M1XCLK (0)
#define SM501_CLOCK_M1XCLK 0
/* config 2 */
#define SM501_PCI_MASTER_BASE (0x000058)
#define SM501_ENDIAN_CONTROL (0x00005C)
#define SM501_DEVICEID (0x000060)
#define SM501_PCI_MASTER_BASE 0x000058
#define SM501_ENDIAN_CONTROL 0x00005C
#define SM501_DEVICEID 0x000060
/* 0x050100A0 */
#define SM501_DEVICEID_SM501 (0x05010000)
#define SM501_DEVICEID_IDMASK (0xffff0000)
#define SM501_DEVICEID_REVMASK (0x000000ff)
#define SM501_DEVICEID_SM501 0x05010000
#define SM501_DEVICEID_IDMASK 0xffff0000
#define SM501_DEVICEID_REVMASK 0x000000ff
#define SM501_PLLCLOCK_COUNT (0x000064)
#define SM501_MISC_TIMING (0x000068)
#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
#define SM501_PLLCLOCK_COUNT 0x000064
#define SM501_MISC_TIMING 0x000068
#define SM501_CURRENT_SDRAM_CLOCK 0x00006C
#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
#define SM501_PROGRAMMABLE_PLL_CONTROL 0x000074
/* GPIO base */
#define SM501_GPIO (0x010000)
#define SM501_GPIO_DATA_LOW (0x00)
#define SM501_GPIO_DATA_HIGH (0x04)
#define SM501_GPIO_DDR_LOW (0x08)
#define SM501_GPIO_DDR_HIGH (0x0C)
#define SM501_GPIO_IRQ_SETUP (0x10)
#define SM501_GPIO_IRQ_STATUS (0x14)
#define SM501_GPIO_IRQ_RESET (0x14)
#define SM501_GPIO 0x010000
#define SM501_GPIO_DATA_LOW 0x00
#define SM501_GPIO_DATA_HIGH 0x04
#define SM501_GPIO_DDR_LOW 0x08
#define SM501_GPIO_DDR_HIGH 0x0C
#define SM501_GPIO_IRQ_SETUP 0x10
#define SM501_GPIO_IRQ_STATUS 0x14
#define SM501_GPIO_IRQ_RESET 0x14
/* I2C controller base */
#define SM501_I2C (0x010040)
#define SM501_I2C_BYTE_COUNT (0x00)
#define SM501_I2C_CONTROL (0x01)
#define SM501_I2C_STATUS (0x02)
#define SM501_I2C_RESET (0x02)
#define SM501_I2C_SLAVE_ADDRESS (0x03)
#define SM501_I2C_DATA (0x04)
#define SM501_I2C 0x010040
#define SM501_I2C_BYTE_COUNT 0x00
#define SM501_I2C_CONTROL 0x01
#define SM501_I2C_STATUS 0x02
#define SM501_I2C_RESET 0x02
#define SM501_I2C_SLAVE_ADDRESS 0x03
#define SM501_I2C_DATA 0x04
#define SM501_I2C_CONTROL_START (1 << 2)
#define SM501_I2C_CONTROL_ENABLE (1 << 0)
@ -204,25 +204,25 @@
#define SM501_I2C_RESET_ERROR (1 << 2)
/* SSP base */
#define SM501_SSP (0x020000)
#define SM501_SSP 0x020000
/* Uart 0 base */
#define SM501_UART0 (0x030000)
#define SM501_UART0 0x030000
/* Uart 1 base */
#define SM501_UART1 (0x030020)
#define SM501_UART1 0x030020
/* USB host port base */
#define SM501_USB_HOST (0x040000)
#define SM501_USB_HOST 0x040000
/* USB slave/gadget base */
#define SM501_USB_GADGET (0x060000)
#define SM501_USB_GADGET 0x060000
/* USB slave/gadget data port base */
#define SM501_USB_GADGET_DATA (0x070000)
#define SM501_USB_GADGET_DATA 0x070000
/* Display controller/video engine base */
#define SM501_DC (0x080000)
#define SM501_DC 0x080000
/* common defines for the SM501 address registers */
#define SM501_ADDR_FLIP (1 << 31)
@ -237,12 +237,12 @@
#define SM501_FIFO_11 (0x3 << 16)
/* common registers for panel and the crt */
#define SM501_OFF_DC_H_TOT (0x000)
#define SM501_OFF_DC_V_TOT (0x008)
#define SM501_OFF_DC_H_SYNC (0x004)
#define SM501_OFF_DC_V_SYNC (0x00C)
#define SM501_OFF_DC_H_TOT 0x000
#define SM501_OFF_DC_V_TOT 0x008
#define SM501_OFF_DC_H_SYNC 0x004
#define SM501_OFF_DC_V_SYNC 0x00C
#define SM501_DC_PANEL_CONTROL (0x000)
#define SM501_DC_PANEL_CONTROL 0x000
#define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
#define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
@ -277,65 +277,65 @@
#define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
#define SM501_DC_PANEL_COLOR_KEY (0x008)
#define SM501_DC_PANEL_FB_ADDR (0x00C)
#define SM501_DC_PANEL_FB_OFFSET (0x010)
#define SM501_DC_PANEL_FB_WIDTH (0x014)
#define SM501_DC_PANEL_FB_HEIGHT (0x018)
#define SM501_DC_PANEL_TL_LOC (0x01C)
#define SM501_DC_PANEL_BR_LOC (0x020)
#define SM501_DC_PANEL_H_TOT (0x024)
#define SM501_DC_PANEL_H_SYNC (0x028)
#define SM501_DC_PANEL_V_TOT (0x02C)
#define SM501_DC_PANEL_V_SYNC (0x030)
#define SM501_DC_PANEL_CUR_LINE (0x034)
#define SM501_DC_PANEL_PANNING_CONTROL 0x004
#define SM501_DC_PANEL_COLOR_KEY 0x008
#define SM501_DC_PANEL_FB_ADDR 0x00C
#define SM501_DC_PANEL_FB_OFFSET 0x010
#define SM501_DC_PANEL_FB_WIDTH 0x014
#define SM501_DC_PANEL_FB_HEIGHT 0x018
#define SM501_DC_PANEL_TL_LOC 0x01C
#define SM501_DC_PANEL_BR_LOC 0x020
#define SM501_DC_PANEL_H_TOT 0x024
#define SM501_DC_PANEL_H_SYNC 0x028
#define SM501_DC_PANEL_V_TOT 0x02C
#define SM501_DC_PANEL_V_SYNC 0x030
#define SM501_DC_PANEL_CUR_LINE 0x034
#define SM501_DC_VIDEO_CONTROL (0x040)
#define SM501_DC_VIDEO_FB0_ADDR (0x044)
#define SM501_DC_VIDEO_FB_WIDTH (0x048)
#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
#define SM501_DC_VIDEO_TL_LOC (0x050)
#define SM501_DC_VIDEO_BR_LOC (0x054)
#define SM501_DC_VIDEO_SCALE (0x058)
#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
#define SM501_DC_VIDEO_FB1_ADDR (0x064)
#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
#define SM501_DC_VIDEO_CONTROL 0x040
#define SM501_DC_VIDEO_FB0_ADDR 0x044
#define SM501_DC_VIDEO_FB_WIDTH 0x048
#define SM501_DC_VIDEO_FB0_LAST_ADDR 0x04C
#define SM501_DC_VIDEO_TL_LOC 0x050
#define SM501_DC_VIDEO_BR_LOC 0x054
#define SM501_DC_VIDEO_SCALE 0x058
#define SM501_DC_VIDEO_INIT_SCALE 0x05C
#define SM501_DC_VIDEO_YUV_CONSTANTS 0x060
#define SM501_DC_VIDEO_FB1_ADDR 0x064
#define SM501_DC_VIDEO_FB1_LAST_ADDR 0x068
#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
#define SM501_DC_VIDEO_ALPHA_CONTROL 0x080
#define SM501_DC_VIDEO_ALPHA_FB_ADDR 0x084
#define SM501_DC_VIDEO_ALPHA_FB_OFFSET 0x088
#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR 0x08C
#define SM501_DC_VIDEO_ALPHA_TL_LOC 0x090
#define SM501_DC_VIDEO_ALPHA_BR_LOC 0x094
#define SM501_DC_VIDEO_ALPHA_SCALE 0x098
#define SM501_DC_VIDEO_ALPHA_INIT_SCALE 0x09C
#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY 0x0A0
#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP 0x0A4
#define SM501_DC_PANEL_HWC_BASE (0x0F0)
#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
#define SM501_DC_PANEL_HWC_LOC (0x0F4)
#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
#define SM501_DC_PANEL_HWC_BASE 0x0F0
#define SM501_DC_PANEL_HWC_ADDR 0x0F0
#define SM501_DC_PANEL_HWC_LOC 0x0F4
#define SM501_DC_PANEL_HWC_COLOR_1_2 0x0F8
#define SM501_DC_PANEL_HWC_COLOR_3 0x0FC
#define SM501_HWC_EN (1 << 31)
#define SM501_OFF_HWC_ADDR (0x00)
#define SM501_OFF_HWC_LOC (0x04)
#define SM501_OFF_HWC_COLOR_1_2 (0x08)
#define SM501_OFF_HWC_COLOR_3 (0x0C)
#define SM501_OFF_HWC_ADDR 0x00
#define SM501_OFF_HWC_LOC 0x04
#define SM501_OFF_HWC_COLOR_1_2 0x08
#define SM501_OFF_HWC_COLOR_3 0x0C
#define SM501_DC_ALPHA_CONTROL (0x100)
#define SM501_DC_ALPHA_FB_ADDR (0x104)
#define SM501_DC_ALPHA_FB_OFFSET (0x108)
#define SM501_DC_ALPHA_TL_LOC (0x10C)
#define SM501_DC_ALPHA_BR_LOC (0x110)
#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
#define SM501_DC_ALPHA_CONTROL 0x100
#define SM501_DC_ALPHA_FB_ADDR 0x104
#define SM501_DC_ALPHA_FB_OFFSET 0x108
#define SM501_DC_ALPHA_TL_LOC 0x10C
#define SM501_DC_ALPHA_BR_LOC 0x110
#define SM501_DC_ALPHA_CHROMA_KEY 0x114
#define SM501_DC_ALPHA_COLOR_LOOKUP 0x118
#define SM501_DC_CRT_CONTROL (0x200)
#define SM501_DC_CRT_CONTROL 0x200
#define SM501_DC_CRT_CONTROL_TVP (1 << 15)
#define SM501_DC_CRT_CONTROL_CP (1 << 14)
@ -353,89 +353,89 @@
#define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
#define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
#define SM501_DC_CRT_FB_ADDR (0x204)
#define SM501_DC_CRT_FB_OFFSET (0x208)
#define SM501_DC_CRT_H_TOT (0x20C)
#define SM501_DC_CRT_H_SYNC (0x210)
#define SM501_DC_CRT_V_TOT (0x214)
#define SM501_DC_CRT_V_SYNC (0x218)
#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
#define SM501_DC_CRT_CUR_LINE (0x220)
#define SM501_DC_CRT_MONITOR_DETECT (0x224)
#define SM501_DC_CRT_FB_ADDR 0x204
#define SM501_DC_CRT_FB_OFFSET 0x208
#define SM501_DC_CRT_H_TOT 0x20C
#define SM501_DC_CRT_H_SYNC 0x210
#define SM501_DC_CRT_V_TOT 0x214
#define SM501_DC_CRT_V_SYNC 0x218
#define SM501_DC_CRT_SIGNATURE_ANALYZER 0x21C
#define SM501_DC_CRT_CUR_LINE 0x220
#define SM501_DC_CRT_MONITOR_DETECT 0x224
#define SM501_DC_CRT_HWC_BASE (0x230)
#define SM501_DC_CRT_HWC_ADDR (0x230)
#define SM501_DC_CRT_HWC_LOC (0x234)
#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
#define SM501_DC_CRT_HWC_BASE 0x230
#define SM501_DC_CRT_HWC_ADDR 0x230
#define SM501_DC_CRT_HWC_LOC 0x234
#define SM501_DC_CRT_HWC_COLOR_1_2 0x238
#define SM501_DC_CRT_HWC_COLOR_3 0x23C
#define SM501_DC_PANEL_PALETTE (0x400)
#define SM501_DC_PANEL_PALETTE 0x400
#define SM501_DC_VIDEO_PALETTE (0x800)
#define SM501_DC_VIDEO_PALETTE 0x800
#define SM501_DC_CRT_PALETTE (0xC00)
#define SM501_DC_CRT_PALETTE 0xC00
/* Zoom Video port base */
#define SM501_ZVPORT (0x090000)
#define SM501_ZVPORT 0x090000
/* AC97/I2S base */
#define SM501_AC97 (0x0A0000)
#define SM501_AC97 0x0A0000
/* 8051 micro controller base */
#define SM501_UCONTROLLER (0x0B0000)
#define SM501_UCONTROLLER 0x0B0000
/* 8051 micro controller SRAM base */
#define SM501_UCONTROLLER_SRAM (0x0C0000)
#define SM501_UCONTROLLER_SRAM 0x0C0000
/* DMA base */
#define SM501_DMA (0x0D0000)
#define SM501_DMA 0x0D0000
/* 2d engine base */
#define SM501_2D_ENGINE (0x100000)
#define SM501_2D_SOURCE (0x00)
#define SM501_2D_DESTINATION (0x04)
#define SM501_2D_DIMENSION (0x08)
#define SM501_2D_CONTROL (0x0C)
#define SM501_2D_PITCH (0x10)
#define SM501_2D_FOREGROUND (0x14)
#define SM501_2D_BACKGROUND (0x18)
#define SM501_2D_STRETCH (0x1C)
#define SM501_2D_COLOR_COMPARE (0x20)
#define SM501_2D_COLOR_COMPARE_MASK (0x24)
#define SM501_2D_MASK (0x28)
#define SM501_2D_CLIP_TL (0x2C)
#define SM501_2D_CLIP_BR (0x30)
#define SM501_2D_MONO_PATTERN_LOW (0x34)
#define SM501_2D_MONO_PATTERN_HIGH (0x38)
#define SM501_2D_WINDOW_WIDTH (0x3C)
#define SM501_2D_SOURCE_BASE (0x40)
#define SM501_2D_DESTINATION_BASE (0x44)
#define SM501_2D_ALPHA (0x48)
#define SM501_2D_WRAP (0x4C)
#define SM501_2D_STATUS (0x50)
#define SM501_2D_ENGINE 0x100000
#define SM501_2D_SOURCE 0x00
#define SM501_2D_DESTINATION 0x04
#define SM501_2D_DIMENSION 0x08
#define SM501_2D_CONTROL 0x0C
#define SM501_2D_PITCH 0x10
#define SM501_2D_FOREGROUND 0x14
#define SM501_2D_BACKGROUND 0x18
#define SM501_2D_STRETCH 0x1C
#define SM501_2D_COLOR_COMPARE 0x20
#define SM501_2D_COLOR_COMPARE_MASK 0x24
#define SM501_2D_MASK 0x28
#define SM501_2D_CLIP_TL 0x2C
#define SM501_2D_CLIP_BR 0x30
#define SM501_2D_MONO_PATTERN_LOW 0x34
#define SM501_2D_MONO_PATTERN_HIGH 0x38
#define SM501_2D_WINDOW_WIDTH 0x3C
#define SM501_2D_SOURCE_BASE 0x40
#define SM501_2D_DESTINATION_BASE 0x44
#define SM501_2D_ALPHA 0x48
#define SM501_2D_WRAP 0x4C
#define SM501_2D_STATUS 0x50
#define SM501_CSC_Y_SOURCE_BASE (0xC8)
#define SM501_CSC_CONSTANTS (0xCC)
#define SM501_CSC_Y_SOURCE_X (0xD0)
#define SM501_CSC_Y_SOURCE_Y (0xD4)
#define SM501_CSC_U_SOURCE_BASE (0xD8)
#define SM501_CSC_V_SOURCE_BASE (0xDC)
#define SM501_CSC_SOURCE_DIMENSION (0xE0)
#define SM501_CSC_SOURCE_PITCH (0xE4)
#define SM501_CSC_DESTINATION (0xE8)
#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
#define SM501_CSC_DESTINATION_PITCH (0xF0)
#define SM501_CSC_SCALE_FACTOR (0xF4)
#define SM501_CSC_DESTINATION_BASE (0xF8)
#define SM501_CSC_CONTROL (0xFC)
#define SM501_CSC_Y_SOURCE_BASE 0xC8
#define SM501_CSC_CONSTANTS 0xCC
#define SM501_CSC_Y_SOURCE_X 0xD0
#define SM501_CSC_Y_SOURCE_Y 0xD4
#define SM501_CSC_U_SOURCE_BASE 0xD8
#define SM501_CSC_V_SOURCE_BASE 0xDC
#define SM501_CSC_SOURCE_DIMENSION 0xE0
#define SM501_CSC_SOURCE_PITCH 0xE4
#define SM501_CSC_DESTINATION 0xE8
#define SM501_CSC_DESTINATION_DIMENSION 0xEC
#define SM501_CSC_DESTINATION_PITCH 0xF0
#define SM501_CSC_SCALE_FACTOR 0xF4
#define SM501_CSC_DESTINATION_BASE 0xF8
#define SM501_CSC_CONTROL 0xFC
/* 2d engine data port base */
#define SM501_2D_ENGINE_DATA (0x110000)
#define SM501_2D_ENGINE_DATA 0x110000
/* end of register definitions */
#define SM501_HWC_WIDTH (64)
#define SM501_HWC_HEIGHT (64)
#define SM501_HWC_WIDTH 64
#define SM501_HWC_HEIGHT 64
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = {
@ -868,7 +868,7 @@ static void sm501_2d_operation(SM501State *s)
static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
uint32_t ret = 0;
switch (addr) {
@ -928,7 +928,7 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
static void sm501_system_config_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value);
switch (addr) {
@ -996,7 +996,7 @@ static const MemoryRegionOps sm501_system_config_ops = {
static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
uint8_t ret = 0;
switch (addr) {
@ -1023,7 +1023,7 @@ static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size)
static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value);
switch (addr) {
@ -1092,7 +1092,7 @@ static const MemoryRegionOps sm501_i2c_ops = {
static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_palette_read((uint32_t)addr);
@ -1106,7 +1106,7 @@ static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
static void sm501_palette_write(void *opaque, hwaddr addr,
uint32_t value)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_palette_write((uint32_t)addr, value);
@ -1121,7 +1121,7 @@ static void sm501_palette_write(void *opaque, hwaddr addr,
static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
uint32_t ret = 0;
switch (addr) {
@ -1234,7 +1234,7 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value);
switch (addr) {
@ -1379,7 +1379,7 @@ static const MemoryRegionOps sm501_disp_ctrl_ops = {
static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
uint32_t ret = 0;
switch (addr) {
@ -1457,7 +1457,7 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
static void sm501_2d_engine_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value);
switch (addr) {
@ -1644,7 +1644,7 @@ static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width,
static void sm501_update_display(void *opaque)
{
SM501State *s = (SM501State *)opaque;
SM501State *s = opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
DirtyBitmapSnapshot *snap;
int y, c_x = 0, c_y = 0;
@ -1768,7 +1768,8 @@ static const GraphicHwOps sm501_ops = {
static void sm501_reset(SM501State *s)
{
s->system_control = 0x00100000; /* 2D engine FIFO empty */
/* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
/*
* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
* to be determined at reset by GPIO lines which set config bits.
* We hardwire them:
* SH = 0 : Hitachi Ready Polarity == Active Low

7
hw/pci-host/mv64361.c
View File

@ -72,11 +72,6 @@ struct MV64361PCIState {
uint64_t remap[5];
};
static int mv64361_pcihost_map_irq(PCIDevice *pci_dev, int n)
{
return (n + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
}
static void mv64361_pcihost_set_irq(void *opaque, int n, int level)
{
MV64361PCIState *s = opaque;
@ -97,7 +92,7 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
g_free(name);
name = g_strdup_printf("pci.%d", s->index);
h->bus = pci_register_root_bus(dev, name, mv64361_pcihost_set_irq,
mv64361_pcihost_map_irq, dev,
pci_swizzle_map_irq_fn, dev,
&s->mem, &s->io, 0, 4, TYPE_PCI_BUS);
g_free(name);
pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE);

2
hw/pci-host/pnv_phb4.c
View File

@ -1497,7 +1497,7 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
PHB4_PEC_PCI_STK_REGS_COUNT);
/* PHB pass-through */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
snprintf(name, sizeof(name), "xscom-pec-%d.%d-phb-%d",
pec->chip_id, pec->index, stack_no);
pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb),
&pnv_phb4_xscom_ops, phb, name, 0x40);

22
hw/ppc/e500.c
View File

@ -241,7 +241,7 @@ static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0);
gchar *group = g_strdup_printf("%s/queue-group", node);
void *fdt = data->fdt;
@ -643,9 +643,8 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
}
g_free(soc);
if (pms->pbus_dev) {
platform_bus_create_devtree(pms, fdt, mpic);
}
g_free(mpic);
pmc->fixup_devtree(fdt);
@ -659,9 +658,14 @@ done:
if (!dry_run) {
qemu_fdt_dumpdtb(fdt, fdt_size);
cpu_physical_memory_write(addr, fdt, fdt_size);
/* Set machine->fdt for 'dumpdtb' QMP/HMP command */
g_free(machine->fdt);
machine->fdt = fdt;
} else {
g_free(fdt);
}
ret = fdt_size;
g_free(fdt);
out:
g_free(pci_map);
@ -1018,9 +1022,13 @@ void ppce500_init(MachineState *machine)
/* eSDHC */
if (pmc->has_esdhc) {
create_unimplemented_device("esdhc",
pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET,
MPC85XX_ESDHC_REGS_SIZE);
dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(dev, "name", "esdhc");
qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
/*
* Compatible with:

3
hw/ppc/e500plat.c
View File

@ -46,14 +46,11 @@ static void e500plat_machine_device_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
PPCE500MachineState *pms = PPCE500_MACHINE(hotplug_dev);
if (pms->pbus_dev) {
MachineClass *mc = MACHINE_GET_CLASS(pms);
if (device_is_dynamic_sysbus(mc, dev)) {
platform_bus_link_device(pms->pbus_dev, SYS_BUS_DEVICE(dev));
}
}
}
static

16
hw/ppc/pegasos2.c
View File

@ -102,7 +102,8 @@ static void pegasos2_init(MachineState *machine)
CPUPPCState *env;
MemoryRegion *rom = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
PCIDevice *dev, *via;
Object *via;
PCIDevice *dev;
I2CBus *i2c_bus;
const char *fwname = machine->firmware ?: PROM_FILENAME;
char *filename;
@ -159,19 +160,18 @@ static void pegasos2_init(MachineState *machine)
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
/* VIA VT8231 South Bridge (multifunction PCI device) */
via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
TYPE_VT8231_ISA);
via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
true, TYPE_VT8231_ISA));
object_property_add_alias(OBJECT(machine), "rtc-time",
object_resolve_path_component(OBJECT(via),
"rtc"),
object_resolve_path_component(via, "rtc"),
"date");
qdev_connect_gpio_out(DEVICE(via), 0,
qdev_get_gpio_in_named(pm->mv, "gpp", 31));
dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "ide"));
dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
pci_ide_create_devs(dev);
dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "pm"));
dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
spd_data = spd_data_generate(DDR, machine->ram_size);
smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
@ -564,7 +564,7 @@ static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
/* addional devices */
/* additional devices */
g_string_printf(name, "%s/lpt@i3bc", fi->path);
qemu_fdt_add_subnode(fi->fdt, name->str);
qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);

5
include/hw/pci-host/pnv_phb4.h
View File

@ -173,8 +173,6 @@ struct PnvPhb4PecState {
uint32_t index;
uint32_t chip_id;
MemoryRegion *system_memory;
/* Nest registers, excuding per-stack */
#define PHB4_PEC_NEST_REGS_COUNT 0xf
uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
@ -216,8 +214,7 @@ struct PnvPhb4PecClass {
#define PNV_PHB5(obj) \
OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5)
#define PNV_PHB5_VERSION 0x000000a500000001ull
#define PNV_PHB5_DEVICE_ID 0x0652
#define PNV_PHB5_VERSION 0x000000a500000002ull
#define TYPE_PNV_PHB5_PEC "pnv-phb5-pec"
#define PNV_PHB5_PEC(obj) \

28
tests/migration/guestperf/engine.py
View File

@ -281,6 +281,26 @@ class Engine(object):
resp = src.command("stop")
paused = True
def _is_ppc64le(self):
_, _, _, _, machine = os.uname()
if machine == "ppc64le":
return True
return False
def _get_guest_console_args(self):
if self._is_ppc64le():
return "console=hvc0"
else:
return "console=ttyS0"
def _get_qemu_serial_args(self):
if self._is_ppc64le():
return ["-chardev", "stdio,id=cdev0",
"-device", "spapr-vty,chardev=cdev0"]
else:
return ["-chardev", "stdio,id=cdev0",
"-device", "isa-serial,chardev=cdev0"]
def _get_common_args(self, hardware, tunnelled=False):
args = [
"noapic",
@ -289,8 +309,10 @@ class Engine(object):
"noreplace-smp",
"cgroup_disable=memory",
"pci=noearly",
"console=ttyS0",
]
args.append(self._get_guest_console_args())
if self._debug:
args.append("debug")
else:
@ -308,12 +330,12 @@ class Engine(object):
"-kernel", self._kernel,
"-initrd", self._initrd,
"-append", cmdline,
"-chardev", "stdio,id=cdev0",
"-device", "isa-serial,chardev=cdev0",
"-m", str((hardware._mem * 1024) + 512),
"-smp", str(hardware._cpus),
]
argv.extend(self._get_qemu_serial_args())
if self._debug:
argv.extend(["-device", "sga"])

4
tests/migration/meson.build
View File

@ -1,7 +1,9 @@
sysprof = dependency('sysprof-capture-4', required: false)
stress = executable(
'stress',
files('stress.c'),
dependencies: [glib],
dependencies: [glib, sysprof],
link_args: ['-static'],
build_by_default: false,
)