fix spelling in hw sub directory
Correct obvious spelling errors in qemu/hw directory. Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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3a93113a00
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66a0a2cb81
@ -44,7 +44,7 @@ typedef struct V9fsThPool {
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qemu_coroutine_self()); \
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qemu_bh_schedule(co_bh); \
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/* \
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* yeild in qemu thread and re-enter back \
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* yield in qemu thread and re-enter back \
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* in glib worker thread \
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*/ \
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qemu_coroutine_yield(); \
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@ -520,7 +520,7 @@ static int handle_name_to_path(FsContext *ctx, V9fsPath *dir_path,
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}
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fh = g_malloc(sizeof(struct file_handle) + data->handle_bytes);
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fh->handle_bytes = data->handle_bytes;
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/* add a "./" at the begining of the path */
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/* add a "./" at the beginning of the path */
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snprintf(buffer, PATH_MAX, "./%s", name);
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/* flag = 0 imply don't follow symlink */
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ret = name_to_handle(dirfd, buffer, fh, &mnt_id, 0);
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@ -2,7 +2,7 @@
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* QEMU Alpha DP264/CLIPPER hardware system emulator.
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*
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* Choose CLIPPER IRQ mappings over, say, DP264, MONET, or WEBBRICK
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* variants because CLIPPER doesn't have an SMC669 SuperIO controler
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* variants because CLIPPER doesn't have an SMC669 SuperIO controller
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* that we need to emulate as well.
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*/
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@ -602,7 +602,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
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return 0;
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case 0x0c: /* Acknowledge */
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return gic_acknowledge_irq(s, cpu);
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case 0x14: /* Runing Priority */
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case 0x14: /* Running Priority */
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return s->running_priority[cpu];
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case 0x18: /* Highest Pending Interrupt */
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return s->current_pending[cpu];
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@ -222,7 +222,7 @@ static void csrhci_in_packet(struct csrhci_s *s, uint8_t *pkt)
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rpkt = csrhci_out_packet_csr(s, H4_NEG_PKT, 10);
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*rpkt ++ = 0x20; /* Operational settings negotation Ok */
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*rpkt ++ = 0x20; /* Operational settings negotiation Ok */
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memcpy(rpkt, pkt, 7); rpkt += 7;
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*rpkt ++ = 0xff;
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*rpkt = 0xff;
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@ -783,7 +783,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
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s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
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if (s->cirrus_srccounter <= 0)
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goto the_end;
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/* more bytes than needed can be transfered because of
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/* more bytes than needed can be transferred because of
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word alignment, so we keep them for the next line */
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/* XXX: keep alignment to speed up transfer */
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end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
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@ -295,7 +295,7 @@
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#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
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#define E1000_MDPHYA 0x0003C /* PHY address - RW */
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#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
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#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
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#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
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#define E1000_GCR 0x05B00 /* PCI-Ex Control */
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@ -180,7 +180,7 @@ struct fs_dma_channel
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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/* Control registers. */
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uint32_t regs[DMA_REG_MAX];
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};
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@ -53,7 +53,7 @@ static void pic_update(struct etrax_pic *fs)
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
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/* The ETRAX interrupt controller signals interrupts to teh core
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/* The ETRAX interrupt controller signals interrupts to the core
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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@ -715,7 +715,7 @@ static void OPLCloseTable( void )
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free(VIB_TABLE);
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}
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/* CSM Key Controll */
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/* CSM Key Control */
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INLINE void CSMKeyControll(OPL_CH *CH)
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{
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OPL_SLOT *slot1 = &CH->SLOT[SLOT1];
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@ -762,7 +762,7 @@ static void OPLWriteReg(FM_OPL *OPL, int r, int v)
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switch(r&0xe0)
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{
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case 0x00: /* 00-1f:controll */
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case 0x00: /* 00-1f:control */
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switch(r&0x1f)
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{
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case 0x01:
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@ -826,7 +826,7 @@ static void OPLWriteReg(FM_OPL *OPL, int r, int v)
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LOG(LOG_WAR,("OPL:write unmapped KEYBOARD port\n"));
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}
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return;
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case 0x07: /* DELTA-T controll : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
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case 0x07: /* DELTA-T control : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
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if(OPL->type&OPL_TYPE_ADPCM)
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YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
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return;
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@ -1380,7 +1380,7 @@ int OPLTimerOver(FM_OPL *OPL,int c)
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else
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{ /* Timer A */
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OPL_STATUS_SET(OPL,0x40);
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/* CSM mode key,TL controll */
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/* CSM mode key,TL control */
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if( OPL->mode & 0x80 )
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{ /* CSM mode total level latch and auto key on */
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int ch;
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@ -83,7 +83,7 @@ void gus_dma_transferdata(GUSEmuState *state, char *dma_addr, unsigned int count
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/* it is possible to break down a single transfer into multiple ones, but take care that: */
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/* -dma_count is actually count-1 */
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/* -before and during a transfer, DREQ is set and TC cleared */
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/* -when calling gus_dma_transferdata(), TC is only set true for call transfering the last byte */
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/* -when calling gus_dma_transferdata(), TC is only set true for call transferring the last byte */
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/* -after the last transfer, DREQ is cleared and TC is set */
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/* ** GF1 mixer emulation functions: */
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@ -502,7 +502,7 @@ void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int coun
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/* this function gets called by the callback function as soon as a DMA transfer is about to start
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* dma_addr is a translated address within accessible memory, not the physical one,
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* count is (real dma count register)+1
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* note that the amount of bytes transfered is fully determined by values in the DMA registers
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* note that the amount of bytes transferred is fully determined by values in the DMA registers
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* do not forget to update DMA states after transferring the entire block:
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* DREQ cleared & TC asserted after the _whole_ transfer */
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@ -517,7 +517,7 @@ void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int coun
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int offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf);
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if (state->gusdma >= 4)
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offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */
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destaddr = (char *) state->himemaddr + offset; /* wavetable RAM adress */
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destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */
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}
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GUSregw(GUS42DMAStart) += (GUSword) (count >> 4); /* ToDo: add 16bit GUS page limit? */
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@ -1000,7 +1000,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
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printf("ide: CMD=%02x\n", val);
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#endif
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s = idebus_active_if(bus);
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/* ignore commands to non existant slave */
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/* ignore commands to non existent slave */
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if (s != bus->ifs && !s->bs)
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return;
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@ -697,7 +697,7 @@ static uint32_t do_phy_read(lan9118_state *s, int reg)
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return 0x0007;
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case 3: /* ID2 */
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return 0xc0d1;
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case 4: /* Auto-neg advertisment */
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case 4: /* Auto-neg advertisement */
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return s->phy_advertise;
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case 5: /* Auto-neg Link Partner Ability */
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return 0x0f71;
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@ -731,7 +731,7 @@ static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
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s->phy_status |= 0x0020;
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}
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break;
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case 4: /* Auto-neg advertisment */
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case 4: /* Auto-neg advertisement */
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s->phy_advertise = (val & 0x2d7f) | 0x80;
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break;
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/* TODO 17, 18, 27, 31 */
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@ -1616,7 +1616,7 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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case 0x500: /* CM_CLKEN_PLL */
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if (value & 0xffffff30)
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fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
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"future compatiblity\n", __FUNCTION__);
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"future compatibility\n", __FUNCTION__);
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if ((s->clken[9] ^ value) & 0xcc) {
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s->clken[9] &= ~0xcc;
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s->clken[9] |= value & 0xcc;
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@ -1635,7 +1635,7 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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case 0x540: /* CM_CLKSEL1_PLL */
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if (value & 0xfc4000d7)
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fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
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"future compatiblity\n", __FUNCTION__);
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"future compatibility\n", __FUNCTION__);
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if ((s->clksel[5] ^ value) & 0x003fff00) {
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s->clksel[5] = value & 0x03bfff28;
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omap_prcm_dpll_update(s);
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@ -1647,7 +1647,7 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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case 0x544: /* CM_CLKSEL2_PLL */
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if (value & ~3)
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fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
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"future compatiblity\n", __FUNCTION__);
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"future compatibility\n", __FUNCTION__);
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if (s->clksel[6] != (value & 3)) {
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s->clksel[6] = value & 3;
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omap_prcm_dpll_update(s);
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2
hw/pc.c
2
hw/pc.c
@ -983,7 +983,7 @@ void pc_memory_init(MemoryRegion *system_memory,
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linux_boot = (kernel_filename != NULL);
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/* Allocate RAM. We allocate it as a single memory region and use
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* aliases to address portions of it, mostly for backwards compatiblity
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* aliases to address portions of it, mostly for backwards compatibility
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* with older qemus that used qemu_ram_alloc().
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*/
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ram = g_malloc(sizeof(*ram));
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@ -826,7 +826,7 @@ typedef struct PCIEAERErrorName {
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} PCIEAERErrorName;
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/*
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* AER error name -> value convertion table
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* AER error name -> value conversion table
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* This naming scheme is same to linux aer-injection tool.
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*/
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static const struct PCIEAERErrorName pcie_aer_error_list[] = {
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@ -358,7 +358,7 @@ static void pl110_write(void *opaque, target_phys_addr_t offset,
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int n;
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/* For simplicity invalidate the display whenever a control register
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is writen to. */
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is written to. */
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s->invalidate = 1;
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if (offset >= 0x200 && offset < 0x400) {
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/* Pallette. */
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@ -311,9 +311,9 @@ static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
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case 0x48: /* FifoCnt */
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/* The documentation is somewhat vague about exactly what FifoCnt
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does. On real hardware it appears to be when decrememnted
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when a word is transfered between the FIFO and the serial
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when a word is transferred between the FIFO and the serial
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data engine. DataCnt is decremented after each byte is
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transfered between the serial engine and the card.
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transferred between the serial engine and the card.
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We don't emulate this level of detail, so both can be the same. */
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tmp = (s->datacnt + 3) >> 2;
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if (s->linux_hack) {
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@ -157,7 +157,7 @@
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* Exeption-related registers
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*/
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/* Immediate data for TRAPA instuction - TRA */
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/* Immediate data for TRAPA instruction - TRA */
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#define SH7750_TRA_REGOFS 0x000020 /* offset */
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#define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS)
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#define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS)
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@ -141,7 +141,7 @@ typedef struct sPAPREnvironment {
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#define H_DABRX_KERNEL (1ULL<<(63-62))
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#define H_DABRX_USER (1ULL<<(63-63))
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/* Each control block has to be on a 4K bondary */
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/* Each control block has to be on a 4K boundary */
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#define H_CB_ALIGNMENT 4096
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/* pSeries hypervisor opcodes */
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@ -42,7 +42,7 @@ typedef struct IB700state {
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/* This is the timer. We use a global here because the watchdog
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* code ensures there is only one watchdog (it is located at a fixed,
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* unchangable IO port, so there could only ever be one anyway).
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* unchangeable IO port, so there could only ever be one anyway).
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*/
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/* A write to this register enables the timer. */
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