target-sh4: map FP registers as TCG variables
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
9850d1e82c
commit
66ba317c90
@ -72,6 +72,7 @@ static TCGv cpu_gregs[24];
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static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
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static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
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static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
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static TCGv cpu_fregs[32];
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/* internal register indexes */
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static TCGv cpu_flags, cpu_delayed_pc;
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@ -89,6 +90,16 @@ static void sh4_translate_init(void)
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"R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
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"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
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};
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static const char * const fregnames[32] = {
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"FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
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"FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
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"FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
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"FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
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"FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
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"FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
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"FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
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"FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
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};
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if (done_init)
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return;
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@ -97,8 +108,8 @@ static void sh4_translate_init(void)
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for (i = 0; i < 24; i++)
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cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, gregs[i]),
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gregnames[i]);
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offsetof(CPUState, gregs[i]),
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gregnames[i]);
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cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, pc), "PC");
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@ -133,6 +144,11 @@ static void sh4_translate_init(void)
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offsetof(CPUState, delayed_pc),
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"_delayed_pc_");
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for (i = 0; i < 32; i++)
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cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fregs[i]),
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fregnames[i]);
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/* register helpers */
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#define GEN_HELPER 2
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#include "helper.h"
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@ -393,38 +409,19 @@ static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
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tcg_temp_free(tmp);
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}
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static inline void gen_load_fpr32(TCGv_i32 t, int reg)
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{
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
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}
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static inline void gen_load_fpr64(TCGv_i64 t, int reg)
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{
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TCGv_i32 tmp1 = tcg_temp_new_i32();
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TCGv_i32 tmp2 = tcg_temp_new_i32();
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tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
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tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
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tcg_gen_concat_i32_i64(t, tmp2, tmp1);
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tcg_temp_free_i32(tmp1);
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tcg_temp_free_i32(tmp2);
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}
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static inline void gen_store_fpr32(TCGv_i32 t, int reg)
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{
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
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tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
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}
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static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_trunc_i64_i32(tmp, t);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
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tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
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tcg_gen_shri_i64(t, t, 32);
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tcg_gen_trunc_i64_i32(tmp, t);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
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tcg_gen_mov_i32(cpu_fregs[reg], tmp);
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tcg_temp_free_i32(tmp);
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}
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@ -989,10 +986,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_store_fpr64(fp, XREG(B11_8));
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B7_4));
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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}
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return;
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case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
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@ -1002,10 +996,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B7_4));
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tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
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}
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return;
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case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
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@ -1015,10 +1006,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_store_fpr64(fp, XREG(B11_8));
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
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}
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return;
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case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
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@ -1029,10 +1017,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_temp_free_i64(fp);
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tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
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tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
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}
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return;
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@ -1050,13 +1035,9 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
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} else {
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TCGv addr;
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TCGv_i32 fp;
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addr = tcg_temp_new_i32();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B7_4));
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tcg_gen_qemu_st32(fp, addr, ctx->memidx);
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
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tcg_temp_free(addr);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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}
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@ -1071,10 +1052,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_store_fpr64(fp, XREG(B11_8));
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
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}
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tcg_temp_free(addr);
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}
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@ -1089,10 +1067,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_qemu_st64(fp, addr, ctx->memidx);
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B7_4));
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tcg_gen_qemu_st32(fp, addr, ctx->memidx);
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tcg_temp_free_i32(fp);
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tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
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}
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tcg_temp_free(addr);
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}
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@ -1137,36 +1112,26 @@ static void _decode_opc(DisasContext * ctx)
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tcg_temp_free_i64(fp0);
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tcg_temp_free_i64(fp1);
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} else {
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TCGv_i32 fp0, fp1;
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fp0 = tcg_temp_new_i32();
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fp1 = tcg_temp_new_i32();
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gen_load_fpr32(fp0, FREG(B11_8));
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gen_load_fpr32(fp1, FREG(B7_4));
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switch (ctx->opcode & 0xf00f) {
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case 0xf000: /* fadd Rm,Rn */
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gen_helper_fadd_FT(fp0, fp0, fp1);
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gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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break;
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case 0xf001: /* fsub Rm,Rn */
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gen_helper_fsub_FT(fp0, fp0, fp1);
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gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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break;
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case 0xf002: /* fmul Rm,Rn */
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gen_helper_fmul_FT(fp0, fp0, fp1);
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gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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break;
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case 0xf003: /* fdiv Rm,Rn */
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gen_helper_fdiv_FT(fp0, fp0, fp1);
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gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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break;
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case 0xf004: /* fcmp/eq Rm,Rn */
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gen_helper_fcmp_eq_FT(fp0, fp1);
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gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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return;
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case 0xf005: /* fcmp/gt Rm,Rn */
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gen_helper_fcmp_gt_FT(fp0, fp1);
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gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
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return;
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}
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gen_store_fpr32(fp0, FREG(B11_8));
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tcg_temp_free_i32(fp0);
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tcg_temp_free_i32(fp1);
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}
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}
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return;
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@ -1633,18 +1598,12 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
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{
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TCGv fp = tcg_temp_new();
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tcg_gen_mov_i32(fp, cpu_fpul);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free(fp);
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tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
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}
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return;
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case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
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{
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TCGv fp = tcg_temp_new();
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gen_load_fpr32(fp, FREG(B11_8));
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tcg_gen_mov_i32(cpu_fpul, fp);
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tcg_temp_free(fp);
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tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
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}
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return;
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case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
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@ -1658,10 +1617,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_temp_free_i64(fp);
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}
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else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_helper_float_FT(fp, cpu_fpul);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
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}
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return;
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case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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@ -1675,19 +1631,12 @@ static void _decode_opc(DisasContext * ctx)
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tcg_temp_free_i64(fp);
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}
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else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B11_8));
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gen_helper_ftrc_FT(cpu_fpul, fp);
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tcg_temp_free_i32(fp);
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gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
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}
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return;
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case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
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{
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B11_8));
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gen_helper_fneg_T(fp, fp);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
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}
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return;
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case 0xf05d: /* fabs FRn/DRn */
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@ -1700,11 +1649,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_store_fpr64(fp, DREG(B11_8));
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B11_8));
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gen_helper_fabs_FT(fp, fp);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
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}
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return;
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case 0xf06d: /* fsqrt FRn */
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@ -1717,28 +1662,20 @@ static void _decode_opc(DisasContext * ctx)
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gen_store_fpr64(fp, DREG(B11_8));
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tcg_temp_free_i64(fp);
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} else {
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TCGv_i32 fp = tcg_temp_new_i32();
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gen_load_fpr32(fp, FREG(B11_8));
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gen_helper_fsqrt_FT(fp, fp);
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gen_store_fpr32(fp, FREG(B11_8));
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tcg_temp_free_i32(fp);
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gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
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}
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return;
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case 0xf07d: /* fsrra FRn */
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break;
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case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
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if (!(ctx->fpscr & FPSCR_PR)) {
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TCGv_i32 val = tcg_const_i32(0);
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gen_load_fpr32(val, FREG(B11_8));
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tcg_temp_free_i32(val);
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
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return;
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}
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break;
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case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
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if (!(ctx->fpscr & FPSCR_PR)) {
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TCGv_i32 val = tcg_const_i32(0x3f800000);
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gen_load_fpr32(val, FREG(B11_8));
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tcg_temp_free_i32(val);
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
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return;
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}
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break;
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