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tests/tcg/xtensa: conditionalize debug option tests 

Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data breakpoint registers on the corresponding definitions. Use
configured debug interrupt level instead of the hardcoded value to set
up IRQ handler and access debug EPC register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-02-18 06:24:38 -08:00
parent 912f161ff7
commit 66c58ba71b
2 changed files with 21 additions and 9 deletions
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3
tests/tcg/xtensa/macros.inc
View File

@ -97,3 +97,6 @@ test_\name:
movi a3, \addr movi a3, \addr
s32i a3, a2, 0 s32i a3, a2, 0
.endm .endm
#define glue(a, b) _glue(a, b)
#define _glue(a, b) a ## b

27
tests/tcg/xtensa/test_break.S
View File

@ -1,10 +1,13 @@
#include "macros.inc" #include "macros.inc"
#define debug_level 6
#define debug_vector level6
test_suite break test_suite break
#if XCHAL_HAVE_DEBUG
#define debug_level XCHAL_DEBUGLEVEL
#define debug_vector glue(level, XCHAL_DEBUGLEVEL)
#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL)
test break test break
set_vector debug_vector, 0 set_vector debug_vector, 0
rsil a2, debug_level rsil a2, debug_level
@ -21,7 +24,7 @@ test break
and a2, a2, a3 and a2, a2, a3
movi a3, 0x10 | debug_level movi a3, 0x10 | debug_level
assert eq, a2, a3 assert eq, a2, a3
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 1b movi a3, 1b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -45,7 +48,7 @@ test breakn
and a2, a2, a3 and a2, a2, a3
movi a3, 0x10 | debug_level movi a3, 0x10 | debug_level
assert eq, a2, a3 assert eq, a2, a3
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 1b movi a3, 1b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -53,6 +56,7 @@ test breakn
assert eq, a2, a3 assert eq, a2, a3
test_end test_end
#if XCHAL_NUM_IBREAK
test ibreak test ibreak
set_vector debug_vector, 0 set_vector debug_vector, 0
rsil a2, debug_level rsil a2, debug_level
@ -83,7 +87,7 @@ test ibreak
and a2, a2, a3 and a2, a2, a3
movi a3, 0x10 | debug_level movi a3, 0x10 | debug_level
assert eq, a2, a3 assert eq, a2, a3
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 1b movi a3, 1b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -110,7 +114,7 @@ test ibreak_remove
and a2, a2, a3 and a2, a2, a3
movi a3, 0x10 | debug_level movi a3, 0x10 | debug_level
assert eq, a2, a3 assert eq, a2, a3
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 2b movi a3, 2b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -141,6 +145,7 @@ test ibreak_priority
movi a3, 0x2 movi a3, 0x2
assert eq, a2, a3 assert eq, a2, a3
test_end test_end
#endif
test icount test icount
set_vector debug_vector, 2f set_vector debug_vector, 2f
@ -158,7 +163,7 @@ test icount
2: 2:
movi a2, 0 movi a2, 0
wsr a2, icountlevel wsr a2, icountlevel
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 1b movi a3, 1b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -167,7 +172,7 @@ test icount
test_end test_end
.macro check_dbreak dr .macro check_dbreak dr
rsr a2, epc6 rsr a2, EPC_DEBUG
movi a3, 1b movi a3, 1b
assert eq, a2, a3 assert eq, a2, a3
rsr a2, debugcause rsr a2, debugcause
@ -194,6 +199,7 @@ test_end
reset_ps reset_ps
.endm .endm
#if XCHAL_NUM_DBREAK
test dbreak_exact test dbreak_exact
dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
@ -253,5 +259,8 @@ test dbreak_invalid
dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test_end test_end
#endif
#endif
test_suite_end test_suite_end