Partial fix to Sparc32 Linux host global register mangling problem
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3806 c046a42c-6fe2-441c-8c8c-71466251a162
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blueswir1
parent
d07bde88a5
commit
66f1cdbde4
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@ -161,7 +161,7 @@ ifeq ($(ARCH),sparc)
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OP_CFLAGS+=-fno-omit-frame-pointer
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else
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BASE_CFLAGS+=-ffixed-g1 -ffixed-g6
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HELPER_CFLAGS=$(CFLAGS) -ffixed-i0 -mflat
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HELPER_CFLAGS=$(CFLAGS) -ffixed-i0
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# -static is used to avoid g1/g3 usage by the dynamic linker
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BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld -static
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endif
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74
cpu-exec.c
74
cpu-exec.c
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@ -40,6 +40,52 @@ int tb_invalidated_flag;
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#define SAVE_GLOBALS()
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#define RESTORE_GLOBALS()
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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#include <features.h>
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#if defined(__GLIBC__) && ((__GLIBC__ < 2) || \
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((__GLIBC__ == 2) && (__GLIBC_MINOR__ <= 90)))
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// Work around ugly bugs in glibc that mangle global register contents
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static volatile void *saved_env;
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static volatile unsigned long saved_t0, saved_i7;
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#undef SAVE_GLOBALS
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#define SAVE_GLOBALS() do { \
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saved_env = env; \
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saved_t0 = T0; \
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asm volatile ("st %%i7, [%0]" : : "r" (&saved_i7)); \
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} while(0)
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#undef RESTORE_GLOBALS
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#define RESTORE_GLOBALS() do { \
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env = (void *)saved_env; \
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T0 = saved_t0; \
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asm volatile ("ld [%0], %%i7" : : "r" (&saved_i7)); \
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} while(0)
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static int sparc_setjmp(jmp_buf buf)
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{
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int ret;
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SAVE_GLOBALS();
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ret = setjmp(buf);
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RESTORE_GLOBALS();
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return ret;
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}
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#undef setjmp
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#define setjmp(jmp_buf) sparc_setjmp(jmp_buf)
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static void sparc_longjmp(jmp_buf buf, int val)
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{
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SAVE_GLOBALS();
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longjmp(buf, val);
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}
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#define longjmp(jmp_buf, val) sparc_longjmp(jmp_buf, val)
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#endif
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#endif
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void cpu_loop_exit(void)
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{
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/* NOTE: the register at this point must be saved by hand because
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@ -133,7 +179,9 @@ static TranslationBlock *tb_find_slow(target_ulong pc,
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tb->tc_ptr = tc_ptr;
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tb->cs_base = cs_base;
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tb->flags = flags;
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SAVE_GLOBALS();
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cpu_gen_code(env, tb, &code_gen_size);
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RESTORE_GLOBALS();
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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/* check next page if needed */
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@ -232,11 +280,7 @@ static inline TranslationBlock *tb_find_fast(void)
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return tb;
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}
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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#define BREAK_CHAIN tmp_T0 = 0
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#else
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#define BREAK_CHAIN T0 = 0
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#endif
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/* main execution loop */
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@ -248,10 +292,6 @@ int cpu_exec(CPUState *env1)
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#if defined(reg_REGWPTR)
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uint32_t *saved_regwptr;
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#endif
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#endif
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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int saved_i7;
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target_ulong tmp_T0;
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#endif
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int ret, interrupt_request;
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void (*gen_func)(void);
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@ -267,10 +307,7 @@ int cpu_exec(CPUState *env1)
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#define SAVE_HOST_REGS 1
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#include "hostregs_helper.h"
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env = env1;
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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SAVE_GLOBALS();
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env_to_regs();
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#if defined(TARGET_I386)
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@ -380,10 +417,7 @@ int cpu_exec(CPUState *env1)
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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SAVE_GLOBALS();
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interrupt_request = env->interrupt_request;
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if (__builtin_expect(interrupt_request, 0)
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#if defined(TARGET_I386)
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@ -597,9 +631,7 @@ int cpu_exec(CPUState *env1)
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lookup_symbol(tb->pc));
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}
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#endif
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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T0 = tmp_T0;
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#endif
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RESTORE_GLOBALS();
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/* see if we can patch the calling TB. When the TB
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spans two pages, we cannot safely do a direct
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jump. */
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@ -695,9 +727,7 @@ int cpu_exec(CPUState *env1)
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#endif
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/* restore global registers */
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
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#endif
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RESTORE_GLOBALS();
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#include "hostregs_helper.h"
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/* fail safe : never use cpu_single_env outside cpu_exec() */
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@ -1244,12 +1244,14 @@ void OPPROTO op_exception(void)
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{
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env->exception_index = PARAM1;
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cpu_loop_exit();
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FORCE_RET();
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}
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void OPPROTO op_trap_T0(void)
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{
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env->exception_index = TT_TRAP + (T0 & 0x7f);
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cpu_loop_exit();
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FORCE_RET();
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}
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void OPPROTO op_trapcc_T0(void)
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