Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs
This patch conflicts with https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html If that series goes in first, we'll rework this patch and vice versa. Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231210220712.491494-8-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
This commit is contained in:
Taylor Simpson
Brian Cain
parent
c90e3103a3
commit
66fab981c0
@ -23,162 +23,6 @@ import string
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import hex_common
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##
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## Helpers for gen_analyze_func
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##
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def is_predicated(tag):
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return "A_CONDEXEC" in hex_common.attribdict[tag]
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def analyze_opn_old(f, tag, regtype, regid, regno):
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regN = f"{regtype}{regid}N"
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predicated = "true" if is_predicated(tag) else "false"
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if regtype == "R":
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if regid in {"ss", "tt"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
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elif regid in {"dd", "ee", "xx", "yy"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
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elif regid in {"s", "t", "u", "v"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_read(ctx, {regN});\n")
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elif regid in {"d", "e", "x", "y"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "P":
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if regid in {"s", "t", "u", "v"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_pred_read(ctx, {regN});\n")
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elif regid in {"d", "e", "x"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_pred_write(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "C":
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if regid == "ss":
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f.write(
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f" const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n"
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)
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f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
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elif regid == "dd":
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f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
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f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
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elif regid == "s":
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f.write(
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f" const int {regN} = insn->regno[{regno}] "
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"+ HEX_REG_SA0;\n"
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)
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f.write(f" ctx_log_reg_read(ctx, {regN});\n")
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elif regid == "d":
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f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
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f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "M":
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if regid == "u":
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_read(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "V":
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newv = "EXT_DFL"
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if hex_common.is_new_result(tag):
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newv = "EXT_NEW"
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elif hex_common.is_tmp_result(tag):
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newv = "EXT_TMP"
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if regid in {"dd", "xx"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(
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f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
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)
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elif regid in {"uu", "vv"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n")
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elif regid in {"s", "u", "v", "w"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
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elif regid in {"d", "x", "y"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "Q":
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if regid in {"d", "e", "x"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
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elif regid in {"s", "t", "u", "v"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_qreg_read(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "G":
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if regid in {"dd"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"d"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"ss"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"s"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "S":
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if regid in {"dd"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"d"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"ss"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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elif regid in {"s"}:
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f.write(f"// const int {regN} = insn->regno[{regno}];\n")
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else:
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hex_common.bad_register(regtype, regid)
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else:
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hex_common.bad_register(regtype, regid)
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def analyze_opn_new(f, tag, regtype, regid, regno):
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regN = f"{regtype}{regid}N"
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if regtype == "N":
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if regid in {"s", "t"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_reg_read(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "P":
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if regid in {"t", "u", "v"}:
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_pred_read(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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elif regtype == "O":
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if regid == "s":
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f.write(f" const int {regN} = insn->regno[{regno}];\n")
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f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
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else:
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hex_common.bad_register(regtype, regid)
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else:
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hex_common.bad_register(regtype, regid)
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def analyze_opn(f, tag, regtype, regid, i):
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if hex_common.is_pair(regid):
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analyze_opn_old(f, tag, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_old_val(regtype, regid, tag):
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analyze_opn_old(f, tag, regtype, regid, i)
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elif hex_common.is_new_val(regtype, regid, tag):
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analyze_opn_new(f, tag, regtype, regid, i)
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else:
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hex_common.bad_register(regtype, regid)
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else:
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hex_common.bad_register(regtype, regid)
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##
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## Generate the code to analyze the instruction
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## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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@ -203,7 +47,11 @@ def gen_analyze_func(f, tag, regs, imms):
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i = 0
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## Analyze all the registers
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for regtype, regid in regs:
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analyze_opn(f, tag, regtype, regid, i)
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reg = hex_common.get_register(tag, regtype, regid)
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if reg.is_written():
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reg.analyze_write(f, tag, i)
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else:
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reg.analyze_read(f, i)
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i += 1
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has_generated_helper = not hex_common.skip_qemu_helper(
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@ -236,6 +84,7 @@ def main():
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if is_idef_parser_enabled:
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hex_common.read_idef_parser_enabled_file(sys.argv[5])
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hex_common.calculate_attribs()
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hex_common.init_registers()
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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@ -486,6 +486,12 @@ class GprDest(Register, Single, Dest):
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f.write(code_fmt(f"""\
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gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
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"""))
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class GprSource(Register, Single, OldSource):
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def decl_tcg(self, f, tag, regno):
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@ -493,12 +499,22 @@ class GprSource(Register, Single, OldSource):
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = hex_gpr[{self.reg_num}];
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class GprNewSource(Register, Single, NewSource):
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def decl_tcg(self, f, tag, regno):
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = get_result_gpr(ctx, insn->regno[{regno}]);
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class GprReadWrite(Register, Single, ReadWrite):
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def decl_tcg(self, f, tag, regno):
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@ -517,6 +533,12 @@ class GprReadWrite(Register, Single, ReadWrite):
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f.write(code_fmt(f"""\
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gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
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"""))
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class ControlDest(Register, Single, Dest):
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def decl_reg_num(self, f, regno):
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@ -532,6 +554,12 @@ class ControlDest(Register, Single, Dest):
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f.write(code_fmt(f"""\
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gen_write_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
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"""))
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class ControlSource(Register, Single, OldSource):
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def decl_reg_num(self, f, regno):
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@ -544,6 +572,11 @@ class ControlSource(Register, Single, OldSource):
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TCGv {self.reg_tcg()} = tcg_temp_new();
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gen_read_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class ModifierSource(Register, Single, OldSource):
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def decl_reg_num(self, f, regno):
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@ -560,6 +593,11 @@ class ModifierSource(Register, Single, OldSource):
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def idef_arg(self, declared):
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declared.append(self.reg_tcg())
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declared.append("CS")
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read(ctx, {self.reg_num});
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"""))
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class PredDest(Register, Single, Dest):
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def decl_tcg(self, f, tag, regno):
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@ -571,6 +609,11 @@ class PredDest(Register, Single, Dest):
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f.write(code_fmt(f"""\
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gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_pred_write(ctx, {self.reg_num});
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"""))
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class PredSource(Register, Single, OldSource):
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def decl_tcg(self, f, tag, regno):
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@ -578,12 +621,22 @@ class PredSource(Register, Single, OldSource):
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = hex_pred[{self.reg_num}];
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_pred_read(ctx, {self.reg_num});
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"""))
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class PredNewSource(Register, Single, NewSource):
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def decl_tcg(self, f, tag, regno):
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f.write(code_fmt(f"""\
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TCGv {self.reg_tcg()} = get_result_pred(ctx, insn->regno[{regno}]);
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_pred_read(ctx, {self.reg_num});
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"""))
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class PredReadWrite(Register, Single, ReadWrite):
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def decl_tcg(self, f, tag, regno):
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@ -596,6 +649,11 @@ class PredReadWrite(Register, Single, ReadWrite):
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f.write(code_fmt(f"""\
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gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_pred_write(ctx, {self.reg_num});
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"""))
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class PairDest(Register, Pair, Dest):
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def decl_tcg(self, f, tag, regno):
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@ -608,6 +666,12 @@ class PairDest(Register, Pair, Dest):
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f.write(code_fmt(f"""\
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gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
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"""))
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class PairSource(Register, Pair, OldSource):
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def decl_tcg(self, f, tag, regno):
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@ -618,6 +682,11 @@ class PairSource(Register, Pair, OldSource):
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hex_gpr[{self.reg_num}],
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hex_gpr[{self.reg_num} + 1]);
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"""))
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def analyze_read(self, f, regno):
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self.decl_reg_num(f, regno)
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f.write(code_fmt(f"""\
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ctx_log_reg_read_pair(ctx, {self.reg_num});
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"""))
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class PairReadWrite(Register, Pair, ReadWrite):
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def decl_tcg(self, f, tag, regno):
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@ -633,6 +702,12 @@ class PairReadWrite(Register, Pair, ReadWrite):
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f.write(code_fmt(f"""\
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gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
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"""))
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class ControlPairDest(Register, Pair, Dest):
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def decl_reg_num(self, f, regno):
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@ -649,6 +724,12 @@ class ControlPairDest(Register, Pair, Dest):
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f.write(code_fmt(f"""\
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gen_write_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
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"""))
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def analyze_write(self, f, tag, regno):
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self.decl_reg_num(f, regno)
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated});
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"""))
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class ControlPairSource(Register, Pair, OldSource):
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def decl_reg_num(self, f, regno):
|
||||
@ -661,6 +742,11 @@ class ControlPairSource(Register, Pair, OldSource):
|
||||
TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
|
||||
gen_read_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()});
|
||||
"""))
|
||||
def analyze_read(self, f, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_reg_read_pair(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class VRegDest(Register, Hvx, Dest):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -680,6 +766,13 @@ class VRegDest(Register, Hvx, Dest):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
newv = hvx_newv(tag)
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
||||
"""))
|
||||
|
||||
class VRegSource(Register, Hvx, OldSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -696,6 +789,11 @@ class VRegSource(Register, Hvx, OldSource):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_read(self, f, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_read(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class VRegNewSource(Register, Hvx, NewSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -709,6 +807,11 @@ class VRegNewSource(Register, Hvx, NewSource):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_read(self, f, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_read(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class VRegReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -731,6 +834,13 @@ class VRegReadWrite(Register, Hvx, ReadWrite):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
newv = hvx_newv(tag)
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
||||
"""))
|
||||
|
||||
class VRegTmp(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -755,6 +865,13 @@ class VRegTmp(Register, Hvx, ReadWrite):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
newv = hvx_newv(tag)
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
|
||||
"""))
|
||||
|
||||
class VRegPairDest(Register, Hvx, Dest):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -774,6 +891,13 @@ class VRegPairDest(Register, Hvx, Dest):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
newv = hvx_newv(tag)
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
|
||||
"""))
|
||||
|
||||
class VRegPairSource(Register, Hvx, OldSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -797,6 +921,11 @@ class VRegPairSource(Register, Hvx, OldSource):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_read(self, f, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_read_pair(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class VRegPairReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -825,6 +954,13 @@ class VRegPairReadWrite(Register, Hvx, ReadWrite):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
newv = hvx_newv(tag)
|
||||
predicated = "true" if is_predicated(tag) else "false"
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
|
||||
"""))
|
||||
|
||||
class QRegDest(Register, Hvx, Dest):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -844,6 +980,11 @@ class QRegDest(Register, Hvx, Dest):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_qreg_write(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class QRegSource(Register, Hvx, OldSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -861,6 +1002,11 @@ class QRegSource(Register, Hvx, OldSource):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_read(self, f, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_qreg_read(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
class QRegReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
@ -883,6 +1029,11 @@ class QRegReadWrite(Register, Hvx, ReadWrite):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
def analyze_write(self, f, tag, regno):
|
||||
self.decl_reg_num(f, regno)
|
||||
f.write(code_fmt(f"""\
|
||||
ctx_log_qreg_write(ctx, {self.reg_num});
|
||||
"""))
|
||||
|
||||
def init_registers():
|
||||
regs = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user