Supervisor mode implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3267 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -261,16 +261,21 @@ static inline void compute_hflags(CPUState *env)
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MIPS_HFLAG_FPU | MIPS_HFLAG_UM);
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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(env->CP0_Status & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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!(env->hflags & MIPS_HFLAG_DM)) {
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if (env->CP0_Status & (1 << CP0St_UM))
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env->hflags |= MIPS_HFLAG_UM;
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if (env->CP0_Status & (1 << CP0St_R0))
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env->hflags |= MIPS_HFLAG_SM;
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}
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#ifdef TARGET_MIPS64
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if (!(env->hflags & MIPS_HFLAG_UM) ||
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(env->CP0_Status & (1 << CP0St_PX)) ||
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(env->CP0_Status & (1 << CP0St_UX)))
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env->hflags |= MIPS_HFLAG_64;
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#endif
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if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
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if ((env->CP0_Status & (1 << CP0St_CU0)) ||
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(!(env->hflags & MIPS_HFLAG_UM) &&
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!(env->hflags & MIPS_HFLAG_SM)))
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env->hflags |= MIPS_HFLAG_CP0;
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if (env->CP0_Status & (1 << CP0St_CU1))
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env->hflags |= MIPS_HFLAG_FPU;
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@ -106,6 +106,8 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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{
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/* User mode can only access useg/xuseg */
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
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int kernel_mode = !user_mode && !supervisor_mode;
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#ifdef TARGET_MIPS64
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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@ -120,14 +122,6 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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}
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#endif
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#ifdef TARGET_MIPS64
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if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
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return TLBRET_BADADDR;
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#else
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if (user_mode && address > 0x7FFFFFFFUL)
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return TLBRET_BADADDR;
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#endif
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if (address <= (int32_t)0x7FFFFFFFUL) {
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/* useg */
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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@ -150,16 +144,16 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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}
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} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
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/* xsseg */
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if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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if ((supervisor_mode || kernel_mode) &&
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SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
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/* xkphys */
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/* XXX: check supervisor mode */
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if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
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{
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if (kernel_mode && KX &&
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(address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) {
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*physical = address & 0X0000000FFFFFFFFFULL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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@ -167,8 +161,8 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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}
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} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
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/* xkseg */
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/* XXX: check supervisor mode */
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if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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if (kernel_mode && KX &&
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address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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@ -176,22 +170,35 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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#endif
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} else if (address < (int32_t)0xA0000000UL) {
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/* kseg0 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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if (kernel_mode) {
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < (int32_t)0xC0000000UL) {
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/* kseg1 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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if (kernel_mode) {
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < (int32_t)0xE0000000UL) {
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/* kseg2 */
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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/* sseg */
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if (supervisor_mode || kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else {
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/* kseg3 */
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/* XXX: check supervisor mode */
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/* XXX: debug segment is not emulated */
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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if (kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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}
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#if 0
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if (logfile) {
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@ -369,7 +376,7 @@ void do_interrupt (CPUState *env)
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}
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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@ -395,7 +402,7 @@ void do_interrupt (CPUState *env)
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}
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->PC[env->current_tc] = (int32_t)0xBFC00000;
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@ -497,7 +504,7 @@ void do_interrupt (CPUState *env)
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}
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env->CP0_Status |= (1 << CP0St_EXL);
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
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}
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env->hflags &= ~MIPS_HFLAG_BMASK;
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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@ -141,7 +141,7 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.CP0_Status_rw_bitmask = 0x1278FF1F,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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},
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{
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@ -156,7 +156,7 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF17,
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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@ -173,7 +173,7 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF17,
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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/* No DSP implemented. */
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.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
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(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
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