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Supervisor mode implementation, by Aurelien Jarno.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3267 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-09-29 19:21:36 +00:00
parent 544540979c
commit 671880e651
3 changed files with 46 additions and 34 deletions
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13
target-mips/exec.h
View File

@ -261,16 +261,21 @@ static inline void compute_hflags(CPUState *env)
MIPS_HFLAG_FPU | MIPS_HFLAG_UM); MIPS_HFLAG_FPU | MIPS_HFLAG_UM);
if (!(env->CP0_Status & (1 << CP0St_EXL)) && if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) && !(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM) && !(env->hflags & MIPS_HFLAG_DM)) {
(env->CP0_Status & (1 << CP0St_UM))) if (env->CP0_Status & (1 << CP0St_UM))
env->hflags |= MIPS_HFLAG_UM; env->hflags |= MIPS_HFLAG_UM;
if (env->CP0_Status & (1 << CP0St_R0))
env->hflags |= MIPS_HFLAG_SM;
}
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
if (!(env->hflags & MIPS_HFLAG_UM) || if (!(env->hflags & MIPS_HFLAG_UM) ||
(env->CP0_Status & (1 << CP0St_PX)) || (env->CP0_Status & (1 << CP0St_PX)) ||
(env->CP0_Status & (1 << CP0St_UX))) (env->CP0_Status & (1 << CP0St_UX)))
env->hflags |= MIPS_HFLAG_64; env->hflags |= MIPS_HFLAG_64;
#endif #endif
if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM)) if ((env->CP0_Status & (1 << CP0St_CU0)) ||
(!(env->hflags & MIPS_HFLAG_UM) &&
!(env->hflags & MIPS_HFLAG_SM)))
env->hflags |= MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_CP0;
if (env->CP0_Status & (1 << CP0St_CU1)) if (env->CP0_Status & (1 << CP0St_CU1))
env->hflags |= MIPS_HFLAG_FPU; env->hflags |= MIPS_HFLAG_FPU;

61
target-mips/helper.c
View File

@ -106,6 +106,8 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
{ {
/* User mode can only access useg/xuseg */ /* User mode can only access useg/xuseg */
int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
int kernel_mode = !user_mode && !supervisor_mode;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
@ -120,14 +122,6 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
} }
#endif #endif
#ifdef TARGET_MIPS64
if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
return TLBRET_BADADDR;
#else
if (user_mode && address > 0x7FFFFFFFUL)
return TLBRET_BADADDR;
#endif
if (address <= (int32_t)0x7FFFFFFFUL) { if (address <= (int32_t)0x7FFFFFFFUL) {
/* useg */ /* useg */
if (env->CP0_Status & (1 << CP0St_ERL)) { if (env->CP0_Status & (1 << CP0St_ERL)) {
@ -150,16 +144,16 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
} }
} else if (address < 0x7FFFFFFFFFFFFFFFULL) { } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
/* xsseg */ /* xsseg */
if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { if ((supervisor_mode || kernel_mode) &&
SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else { } else {
ret = TLBRET_BADADDR; ret = TLBRET_BADADDR;
} }
} else if (address < 0xBFFFFFFFFFFFFFFFULL) { } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
/* xkphys */ /* xkphys */
/* XXX: check supervisor mode */ if (kernel_mode && KX &&
if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) {
{
*physical = address & 0X0000000FFFFFFFFFULL; *physical = address & 0X0000000FFFFFFFFFULL;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
} else { } else {
@ -167,8 +161,8 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
} }
} else if (address < 0xFFFFFFFF7FFFFFFFULL) { } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
/* xkseg */ /* xkseg */
/* XXX: check supervisor mode */ if (kernel_mode && KX &&
if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else { } else {
ret = TLBRET_BADADDR; ret = TLBRET_BADADDR;
@ -176,22 +170,35 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
#endif #endif
} else if (address < (int32_t)0xA0000000UL) { } else if (address < (int32_t)0xA0000000UL) {
/* kseg0 */ /* kseg0 */
/* XXX: check supervisor mode */ if (kernel_mode) {
*physical = address - (int32_t)0x80000000UL; *physical = address - (int32_t)0x80000000UL;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
} else {
ret = TLBRET_BADADDR;
}
} else if (address < (int32_t)0xC0000000UL) { } else if (address < (int32_t)0xC0000000UL) {
/* kseg1 */ /* kseg1 */
/* XXX: check supervisor mode */ if (kernel_mode) {
*physical = address - (int32_t)0xA0000000UL; *physical = address - (int32_t)0xA0000000UL;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
} else {
ret = TLBRET_BADADDR;
}
} else if (address < (int32_t)0xE0000000UL) { } else if (address < (int32_t)0xE0000000UL) {
/* kseg2 */ /* sseg */
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); if (supervisor_mode || kernel_mode) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} else { } else {
/* kseg3 */ /* kseg3 */
/* XXX: check supervisor mode */
/* XXX: debug segment is not emulated */ /* XXX: debug segment is not emulated */
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); if (kernel_mode) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} }
#if 0 #if 0
if (logfile) { if (logfile) {
@ -369,7 +376,7 @@ void do_interrupt (CPUState *env)
} }
enter_debug_mode: enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM; env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
/* EJTAG probe trap enable is not implemented... */ /* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL))) if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD); env->CP0_Cause &= ~(1 << CP0Ca_BD);
@ -395,7 +402,7 @@ void do_interrupt (CPUState *env)
} }
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM; env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
if (!(env->CP0_Status & (1 << CP0St_EXL))) if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD); env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->PC[env->current_tc] = (int32_t)0xBFC00000; env->PC[env->current_tc] = (int32_t)0xBFC00000;
@ -497,7 +504,7 @@ void do_interrupt (CPUState *env)
} }
env->CP0_Status |= (1 << CP0St_EXL); env->CP0_Status |= (1 << CP0St_EXL);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM; env->hflags &= ~(MIPS_HFLAG_SM | MIPS_HFLAG_UM);
} }
env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) { if (env->CP0_Status & (1 << CP0St_BEV)) {

6
target-mips/translate_init.c
View File

@ -141,7 +141,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32, .SYNCI_Step = 32,
.CCRes = 2, .CCRes = 2,
/* No DSP implemented. */ /* No DSP implemented. */
.CP0_Status_rw_bitmask = 0x1278FF17, .CP0_Status_rw_bitmask = 0x1278FF1F,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
}, },
{ {
@ -156,7 +156,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32, .SYNCI_Step = 32,
.CCRes = 2, .CCRes = 2,
/* No DSP implemented. */ /* No DSP implemented. */
.CP0_Status_rw_bitmask = 0x3678FF17, .CP0_Status_rw_bitmask = 0x3678FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
@ -173,7 +173,7 @@ static mips_def_t mips_defs[] =
.SYNCI_Step = 32, .SYNCI_Step = 32,
.CCRes = 2, .CCRes = 2,
/* No DSP implemented. */ /* No DSP implemented. */
.CP0_Status_rw_bitmask = 0x3678FF17, .CP0_Status_rw_bitmask = 0x3678FF1F,
/* No DSP implemented. */ /* No DSP implemented. */
.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |