target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
c1b876b2e9
commit
6781fa119f
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@ -293,3 +293,64 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
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}
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return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
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}
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/* Pairwise long add: add pairs of adjacent elements into
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* double-width elements in the result (eg _s8 is an 8x8->16 op)
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*/
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uint64_t HELPER(neon_addlp_s8)(uint64_t a)
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{
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uint64_t nsignmask = 0x0080008000800080ULL;
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uint64_t wsignmask = 0x8000800080008000ULL;
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uint64_t elementmask = 0x00ff00ff00ff00ffULL;
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uint64_t tmp1, tmp2;
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uint64_t res, signres;
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/* Extract odd elements, sign extend each to a 16 bit field */
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tmp1 = a & elementmask;
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tmp1 ^= nsignmask;
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tmp1 |= wsignmask;
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tmp1 = (tmp1 - nsignmask) ^ wsignmask;
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/* Ditto for the even elements */
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tmp2 = (a >> 8) & elementmask;
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tmp2 ^= nsignmask;
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tmp2 |= wsignmask;
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tmp2 = (tmp2 - nsignmask) ^ wsignmask;
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/* calculate the result by summing bits 0..14, 16..22, etc,
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* and then adjusting the sign bits 15, 23, etc manually.
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* This ensures the addition can't overflow the 16 bit field.
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*/
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signres = (tmp1 ^ tmp2) & wsignmask;
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res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
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res ^= signres;
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return res;
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}
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uint64_t HELPER(neon_addlp_u8)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x00ff00ff00ff00ffULL;
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tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
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return tmp;
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}
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uint64_t HELPER(neon_addlp_s16)(uint64_t a)
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{
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int32_t reslo, reshi;
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reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
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reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
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return (uint32_t)reslo | (((uint64_t)reshi) << 32);
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}
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uint64_t HELPER(neon_addlp_u16)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x0000ffff0000ffffULL;
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tmp += (a >> 16) & 0x0000ffff0000ffffULL;
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return tmp;
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}
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@ -39,3 +39,7 @@ DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
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DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
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DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
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DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
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DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_FLAGS_1(neon_addlp_u8, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
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@ -81,6 +81,7 @@ typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
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typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
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typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
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typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
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typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
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/* initialize TCG globals. */
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void a64_translate_init(void)
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@ -8456,6 +8457,78 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
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}
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}
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static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
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bool is_q, int size, int rn, int rd)
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{
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/* Implement the pairwise operations from 2-misc:
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* SADDLP, UADDLP, SADALP, UADALP.
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* These all add pairs of elements in the input to produce a
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* double-width result element in the output (possibly accumulating).
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*/
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bool accum = (opcode == 0x6);
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int maxpass = is_q ? 2 : 1;
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int pass;
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TCGv_i64 tcg_res[2];
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if (size == 2) {
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/* 32 + 32 -> 64 op */
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TCGMemOp memop = size + (u ? 0 : MO_SIGN);
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for (pass = 0; pass < maxpass; pass++) {
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TCGv_i64 tcg_op1 = tcg_temp_new_i64();
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TCGv_i64 tcg_op2 = tcg_temp_new_i64();
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tcg_res[pass] = tcg_temp_new_i64();
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read_vec_element(s, tcg_op1, rn, pass * 2, memop);
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read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
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tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
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if (accum) {
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read_vec_element(s, tcg_op1, rd, pass, MO_64);
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tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
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}
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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}
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} else {
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for (pass = 0; pass < maxpass; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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NeonGenOneOpFn *genfn;
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static NeonGenOneOpFn * const fns[2][2] = {
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{ gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
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{ gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
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};
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genfn = fns[size][u];
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tcg_res[pass] = tcg_temp_new_i64();
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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genfn(tcg_res[pass], tcg_op);
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if (accum) {
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read_vec_element(s, tcg_op, rd, pass, MO_64);
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if (size == 0) {
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gen_helper_neon_addl_u16(tcg_res[pass],
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tcg_res[pass], tcg_op);
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} else {
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gen_helper_neon_addl_u32(tcg_res[pass],
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tcg_res[pass], tcg_op);
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}
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}
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tcg_temp_free_i64(tcg_op);
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}
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}
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if (!is_q) {
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tcg_res[1] = tcg_const_i64(0);
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}
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for (pass = 0; pass < 2; pass++) {
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write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
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tcg_temp_free_i64(tcg_res[pass]);
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}
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}
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/* C3.6.17 AdvSIMD two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+-----------+--------+-----+------+------+
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@ -8510,7 +8583,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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return;
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}
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unsupported_encoding(s, insn);
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handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
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return;
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case 0x13: /* SHLL, SHLL2 */
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if (u == 0 || size == 3) {
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