target/arm: Mark up sysregs for HFGRTR bits 24..35
Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 24..35. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
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@ -603,6 +603,18 @@ typedef enum FGTBit {
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DO_BIT(HFGRTR, LORID_EL1),
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DO_BIT(HFGRTR, LORN_EL1),
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DO_BIT(HFGRTR, LORSA_EL1),
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DO_BIT(HFGRTR, MAIR_EL1),
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DO_BIT(HFGRTR, MIDR_EL1),
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DO_BIT(HFGRTR, MPIDR_EL1),
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DO_BIT(HFGRTR, PAR_EL1),
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DO_BIT(HFGRTR, REVIDR_EL1),
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DO_BIT(HFGRTR, SCTLR_EL1),
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DO_BIT(HFGRTR, SCXTNUM_EL1),
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DO_BIT(HFGRTR, SCXTNUM_EL0),
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DO_BIT(HFGRTR, TCR_EL1),
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DO_BIT(HFGRTR, TPIDR_EL1),
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DO_BIT(HFGRTR, TPIDRRO_EL0),
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DO_BIT(HFGRTR, TPIDR_EL0),
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} FGTBit;
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#undef DO_BIT
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@ -2206,6 +2206,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_MAIR_EL1,
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.fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
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.resetvalue = 0 },
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{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
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@ -2349,25 +2350,30 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
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{ .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
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.access = PL0_RW,
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.fgt = FGT_TPIDR_EL0,
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.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
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{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW,
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.fgt = FGT_TPIDR_EL0,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
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offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
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.resetfn = arm_cp_reset_ignore },
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{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
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.access = PL0_R | PL1_W,
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.fgt = FGT_TPIDRRO_EL0,
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.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
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.resetvalue = 0},
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{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
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.access = PL0_R | PL1_W,
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.fgt = FGT_TPIDRRO_EL0,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
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offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
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.resetfn = arm_cp_reset_ignore },
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{ .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
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.access = PL1_RW,
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.fgt = FGT_TPIDR_EL1,
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.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
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{ .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
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.access = PL1_RW,
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@ -4164,6 +4170,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_TCR_EL1,
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.writefn = vmsa_tcr_el12_write,
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.raw_writefn = raw_write,
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.resetvalue = 0,
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@ -5399,6 +5406,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.type = ARM_CP_ALIAS,
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.opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0,
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.fgt = FGT_PAR_EL1,
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.fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
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.writefn = par_write },
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#endif
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@ -7562,10 +7570,12 @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
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{ .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
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.access = PL0_RW, .accessfn = access_scxtnum,
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.fgt = FGT_SCXTNUM_EL0,
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.fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
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{ .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
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.access = PL1_RW, .accessfn = access_scxtnum,
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.fgt = FGT_SCXTNUM_EL1,
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.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
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{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
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@ -8604,6 +8614,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
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.fgt = FGT_MIDR_EL1,
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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.readfn = midr_read },
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/* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
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@ -8614,6 +8625,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
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.access = PL1_R,
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.accessfn = access_aa64_tid1,
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.fgt = FGT_REVIDR_EL1,
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.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
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};
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ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
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@ -8785,6 +8797,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARMCPRegInfo mpidr_cp_reginfo[] = {
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{ .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
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.fgt = FGT_MPIDR_EL1,
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.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
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};
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#ifdef CONFIG_USER_ONLY
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@ -8884,6 +8897,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.name = "SCTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fgt = FGT_SCTLR_EL1,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
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offsetof(CPUARMState, cp15.sctlr_ns) },
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.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
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