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arm: Remove system_clock_scale global 

All the devices that used to use system_clock_scale have now been
converted to use Clock inputs instead, so the global is no longer
needed; remove it and all the code that sets it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-08-12 10:33:56 +01:00
parent d18fdd69d0
commit 683754c7b6
10 changed files with 5 additions and 55 deletions
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17
hw/arm/armsse.c
View File

@ -689,17 +689,6 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
}
static void armsse_mainclk_update(void *opaque, ClockEvent event)
{
ARMSSE *s = ARM_SSE(opaque);
/*
* Set system_clock_scale from our Clock input; this is what
* controls the tick rate of the CPU SysTick timer.
*/
system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
}
static void armsse_init(Object *obj)
{
ARMSSE *s = ARM_SSE(obj);
@ -711,8 +700,7 @@ static void armsse_init(Object *obj)
assert(info->sram_banks <= MAX_SRAM_BANKS);
assert(info->num_cpus <= SSE_MAX_CPUS);
s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
armsse_mainclk_update, s, ClockUpdate);
s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0);
s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0);
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
@ -1654,9 +1642,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* devices in the ARMSSE.
*/
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
/* Set initial system_clock_scale from MAINCLK */
armsse_mainclk_update(s, ClockUpdate);
}
static void armsse_idau_check(IDAUInterface *ii, uint32_t address,

2
hw/arm/mps2.c
View File

@ -439,8 +439,6 @@ static void mps2_common_init(MachineState *machine)
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
0x400000);
}

2
hw/arm/msf2-soc.c
View File

@ -144,8 +144,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
system_clock_scale = clock_ticks_to_ns(s->m3clk, 1);
for (i = 0; i < MSF2_NUM_UARTS; i++) {
if (serial_hd(i)) {
serial_mm_init(get_system_memory(), uart_addr[i], 2,

2
hw/arm/netduino2.c
View File

@ -39,8 +39,6 @@ static void netduino2_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);

2
hw/arm/netduinoplus2.c
View File

@ -39,8 +39,6 @@ static void netduinoplus2_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);

2
hw/arm/nrf51_soc.c
View File

@ -84,8 +84,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
* will always provide one).
*/
system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {

7
hw/arm/stellaris.c
View File

@ -263,17 +263,18 @@ static bool ssys_use_rcc2(ssys_state *s)
*/
static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
{
int period_ns;
/*
* SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
* clock is 200MHz, which is a period of 5 ns. Dividing the clock
* frequency by X is the same as multiplying the period by X.
*/
if (ssys_use_rcc2(s)) {
system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
} else {
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
}
clock_set_ns(s->sysclk, system_clock_scale);
clock_set_ns(s->sysclk, period_ns);
if (propagate_clock) {
clock_propagate(s->sysclk);
}

2
hw/arm/stm32vldiscovery.c
View File

@ -42,8 +42,6 @@ static void stm32vldiscovery_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);

2
hw/timer/armv7m_systick.c
View File

@ -30,8 +30,6 @@
#define SYSCALIB_SKEW (1U << 30)
#define SYSCALIB_TENMS ((1U << 24) - 1)
int system_clock_scale;
static void systick_set_period_from_clock(SysTickState *s)
{
/*

22
include/hw/timer/armv7m_systick.h
View File

@ -47,26 +47,4 @@ struct SysTickState {
Clock *cpuclk;
};
/*
* Multiplication factor to convert from system clock ticks to qemu timer
* ticks. This should be set (by board code, usually) to a value
* equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
* in Hz of the CPU.
*
* This value is used by the systick device when it is running in
* its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
* set how fast the timer should tick.
*
* TODO: we should refactor this so that rather than using a global
* we use a device property or something similar. This is complicated
* because (a) the property would need to be plumbed through from the
* board code down through various layers to the systick device
* and (b) the property needs to be modifiable after realize, because
* the stellaris board uses this to implement the behaviour where the
* guest can reprogram the PLL registers to downclock the CPU, and the
* systick device needs to react accordingly. Possibly this should
* be deferred until we have a good API for modelling clock trees.
*/
extern int system_clock_scale;
#endif