target/i386: use mmu_translate for NPT walk
Unify the duplicate code between get_hphys and mmu_translate, by simply making get_hphys call mmu_translate. This also fixes the support for 5-level nested page tables. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
33ce155c67
commit
68746930ae
@ -54,210 +54,6 @@ int get_pg_mode(CPUX86State *env)
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return pg_mode;
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}
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint64_t ptep, pte;
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uint64_t exit_info_1 = 0;
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target_ulong pde_addr, pte_addr;
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uint32_t page_offset;
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int page_size;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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if (!(env->nested_pg_mode & PG_MODE_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (env->nested_pg_mode & PG_MODE_PAE) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (env->nested_pg_mode & PG_MODE_LMA) {
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uint64_t pml5e;
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uint64_t pml4e_addr, pml4e;
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pml5e = env->nested_cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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pml4e_addr = (pml5e & PG_ADDRESS_MASK) +
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(((gphys >> 39) & 0x1ff) << 3);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = (pml4e & PG_ADDRESS_MASK) +
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(((gphys >> 30) & 0x1ff) << 3);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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}
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} else
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#endif
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{
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pdpe_addr = (env->nested_cr3 & ~0x1f) + ((gphys >> 27) & 0x18);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pdpe & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pde_addr = (pdpe & PG_ADDRESS_MASK) + (((gphys >> 21) & 0x1ff) << 3);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pde & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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}
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/* 4 KB page */
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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pte_addr = (pde & PG_ADDRESS_MASK) + (((gphys >> 12) & 0x1ff) << 3);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = (env->nested_cr3 & ~0xfff) + ((gphys >> 20) & 0xffc);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pde | PG_NX_MASK;
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/* if host cr4 PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (env->nested_pg_mode & PG_MODE_PSE)) {
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page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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/* page directory entry */
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pte_addr = (pde & ~0xfff) + ((gphys >> 10) & 0xffc);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep ^= PG_NX_MASK;
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if (!(ptep & PG_USER_MASK)) {
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goto do_fault_protect;
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}
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if (ptep & PG_NX_MASK) {
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if (access_type == MMU_INST_FETCH) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_EXEC;
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}
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if (!(ptep & PG_RW_MASK)) {
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if (access_type == MMU_DATA_STORE) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_WRITE;
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}
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pte &= PG_ADDRESS_MASK & ~(page_size - 1);
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page_offset = gphys & (page_size - 1);
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return pte + page_offset;
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do_fault_rsvd:
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exit_info_1 |= PG_ERROR_RSVD_MASK;
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do_fault_protect:
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exit_info_1 |= PG_ERROR_P_MASK;
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do_fault:
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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exit_info_1 |= PG_ERROR_U_MASK;
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if (access_type == MMU_DATA_STORE) {
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exit_info_1 |= PG_ERROR_W_MASK;
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} else if (access_type == MMU_INST_FETCH) {
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exit_info_1 |= PG_ERROR_I_D_MASK;
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}
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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#define PG_ERROR_OK (-1)
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typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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@ -266,9 +62,9 @@ typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr gphys, MMUAccessType acc
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#define GET_HPHYS(cs, gpa, access_type, prot) \
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(get_hphys_func ? get_hphys_func(cs, gpa, access_type, prot) : gpa)
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static int mmu_translate(CPUState *cs, vaddr addr, MMUTranslateFunc get_hphys_func,
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static int mmu_translate(CPUState *cs, hwaddr addr, MMUTranslateFunc get_hphys_func,
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uint64_t cr3, int is_write1, int mmu_idx, int pg_mode,
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vaddr *xlat, int *page_size, int *prot)
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hwaddr *xlat, int *page_size, int *prot)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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@ -562,6 +358,39 @@ do_check_protect_pse36:
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return error_code;
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}
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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uint64_t exit_info_1;
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int page_size;
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int next_prot;
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hwaddr hphys;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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exit_info_1 = mmu_translate(cs, gphys, NULL, env->nested_cr3,
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access_type, MMU_USER_IDX, env->nested_pg_mode,
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&hphys, &page_size, &next_prot);
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if (exit_info_1 == PG_ERROR_OK) {
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if (prot) {
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*prot &= next_prot;
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}
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return hphys;
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}
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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/* return value:
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* -1 = cannot handle fault
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* 0 = nothing more to do
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@ -575,7 +404,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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int error_code = PG_ERROR_OK;
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int pg_mode, prot, page_size;
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hwaddr paddr;
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target_ulong vaddr;
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hwaddr vaddr;
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#if defined(DEBUG_MMU)
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printf("MMU fault: addr=%" VADDR_PRIx " w=%d mmu=%d eip=" TARGET_FMT_lx "\n",
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